A 146-mm2 8-gb multi-level NAND flash memory with 70-nm CMOS technology. - Takahiko Hara; Koichi Fukuda; Kazuhisa Kanazawa; Noboru Shibata; Koji Hosono; Hiroshi Maejima; Michio Nakagawa; Takumi Abe; Masatsugu Kojima; Masaki Fujiu; Yoshiaki Takeuchi; Kazumi Amemiya; et al. (IEEE J. Solid State Circuits, 2006)

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory. - Noboru Shibata; Hiroshi Maejima; Katsuaki Isobe; Kiyoaki Iwasa; Michio Nakagawa; Masaki Fujiu; Takahiro Shimizu; Mitsuaki Honma; Satoru Hoshi; Toshimasa Kawaai; Kazunori Kanebako; Susumu Yoshikawa; et al. (IEEE J. Solid State Circuits, 2008)

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS. - Cuong Trinh; Noboru Shibata; Takeshi Nakano; Mikio Ogawa; Jumpei Sato; Yoshikazu Takeyama; Katsuaki Isobe; Binh Le; Farookh Moogat; Nima Mokhlesi; Kenji Kozakai; Patrick Hong; et al. (ISSCC, 2009)

A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. - Noboru Shibata; Kazushige Kanda; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Kazuko Inuzuka; Naoaki Kanagawa; Yasuyuki Kajitani; et al. (ISSCC, 2012)

An Embedded DRAM Technology for High-Performance NAND Flash Memories. - Daisaburo Takashima; Mitsuhiro Noguchi; Noboru Shibata; Kazushige Kanda; Hiroshi Sukegawa; Shuso Fujii (IEEE J. Solid State Circuits, 2012)

A 19 nm 112.8 mm2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface. - Kazushige Kanda; Noboru Shibata; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Naoaki Kanagawa; Yasuyuki Kajitani; Takeshi Ogawa; et al. (IEEE J. Solid State Circuits, 2013)

A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. - Hiroshi Maejima; Kazushige Kanda; Susumu Fujimura; Teruo Takagiwa; Susumu Ozawa; Jumpei Sato; Yoshihiko Shindo; Manabu Sato; Naoaki Kanagawa; Junji Musha; Satoshi Inoue; Katsuaki Sakurai; et al. (ISSCC, 2018)

A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Kazushige Kanda; Takahiro Shimizu; Jun Nakai; Osamu Nagao; Naoki Kobayashi 004; Makoto Miakashi; Yasushi Nagadomi; Takeshi Nakano; Takahisa Kawabe; Taira Shibuya; Mario Sako; et al. (ISSCC, 2019)

A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology. - Chang Hua Siau; Kwang-Ho Kim; Seungpil Lee; Katsuaki Isobe; Noboru Shibata; Kapil Verma; Takuya Ariki; Jason Li 001; Jong Yuh; Anirudh Amarnath; Qui Nguyen; Ohwon Kwon; et al. (ISSCC, 2019)

A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Takahisa Kawabe; Taira Shibuya; Mario Sako; Kosuke Yanagidaira; Toshifumi Hashimoto; Hiroki Date; Manabu Sato; Tomoki Nakagawa; Junji Musha; Takatoshi Minamoto; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 2020)

A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface. - Jong Yuh; Jason Li 001; Heguang Li; Yoshihiro Oyama; Cynthia Hsu; Pradeep Anantula; Stanley Jeong; Anirudh Amarnath; Siddhesh Darne; Sneha Bhatia; Tianyu Tang; Aditya Arya; et al. (ISSCC, 2022)

7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technology. - Noboru Shibata; Hironori Uchikawa; Taira Shibuya; Kenri Nakai; Kosuke Yanagidaira; Hirofumi Inoue (IMW, 2023)

A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface. - Jonghak Yuh; Yen-Lung Jason Li; Heguang Li; Yoshihiro Oyama; Cynthia Hsu; Pradeep Anantula; Gwang Yeong Stanley Jeong; Anirudh Amarnath; Siddhesh Darne; Sneha Bhatia; Tianyu Tang; Aditya Arya; et al. (IEEE J. Solid State Circuits, 2023)

Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory. - Noboru Shibata; Hironori Uchikawa; Taira Shibuya; Hirofumi Inoue (IMW, 2024)

Fast Readable Multi-Cell Coding for Flash Memory. - Hironori Uchikawa; Noboru Shibata; Taira Shibuya (ISIT, 2024)