Network Performance of the Prodigy Parallel AI Machine. - Takashi Suzuoka; Noboru Tanabe; Sadao Nakamura; Sumikazu Fujita; Shigeru Oyanagi (Syst. Comput. Jpn., 1989)

Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY. - Noboru Tanabe; Takashi Suzuoka; Sadao Nakamura; Yasushi Kawakura; Shigeru Oyanagi (ICPP (1), 1991)

Implementation of the prodigy parallel AI machine and performance evaluation of communication. - Noboru Tanabe; Sadao Nakamura; Takashi Suzuoka; Shigeru Oyanagi (Syst. Comput. Jpn., 1992)

Improving the performance of global communication on a three-dimensional torus network. - Yasushi Kawakura; Noboru Tanabe; Shigeru Oyanagi (Syst. Comput. Jpn., 1996)

MEMOnet : Network interface plugged into a memory slot. - Noboru Tanabe; Junji Yamamoto; Hiroaki Nishi; Tomohiro Kudoh; Yoshihiro Hamada; Hironori Nakajo; Hideharu Amano (CLUSTER, 2000)

On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. - Noboru Tanabe; Junji Yamamoto; Hiroaki Nishi; Tomohiro Kudoh; Yoshihiro Hamada; Hironori Nakajo; Hideharu Amano (ISPAN, 2000)

Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. - Noboru Tanabe; Yoshihiro Hamada; Hironori Nakajo; Hideki Imashiro; Junji Yamamoto; Tomohiro Kudoh; Hideharu Amano (PARELEC, 2002)

Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. - Noboru Tanabe; Junji Yamamoto; Hiroaki Nishi; Tomohiro Kudoh; Yoshihiro Hamada; Hironori Nakajo; Hideharu Amano (Clust. Comput., 2002)

A New Memory Module for Memory Intensive Applications. - Noboru Tanabe; Hironori Nakajo; Hirotaka Hakozaki; Masasige Nakatake; Yasunori Dohi; Hideharu Amano (PARELEC, 2004)

Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. - Yasuo Miyabe; Akira Kitamura; Yoshihiro Hamada; Tomotaka Miyashiro; Tetsu Izawa; Noboru Tanabe; Hironori Nakajo; Hideharu Amano (ISHPC, 2005)

Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. - Akira Kitamura; Yasuo Miyabe; Tetsu Izawa; Tomotaka Miyashiro; Konosuke Watanabe; Tomohiro Otsuka; Hideharu Amano; Yoshihiro Hamada; Noboru Tanabe; Hironori Nakajo (PDCAT, 2005)

A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. - Yoshihiro Hamada; Hiroaki Nishi; Akira Kitamura; Noboru Tanabe; Hideharu Amano; Hironori Nakajo (PDPTA, 2005)

DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. - Tomotaka Miyashiro; Akira Kitamura; Hironori Nakajo; Noboru Tanabe (FPL, 2006)

Implementation of PC Cluster System with Memory Mapped File by Commodity OS. - Jun Kanai; Takuro Mori; Takeshi Araki; Noboru Tanabe; Hironori Nakajo; Mitaro Namiki (PDPTA, 2006)

Performance evaluation on low-latency communication mechanism of DIMMnet-2. - Akira Kitamura; Yasuo Miyabe; Tomotaka Miyashiro; Noboru Tanabe; Hironori Nakajo; Hideharu Amano (Parallel and Distributed Computing and Networks, 2007)

Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. - Atsushi Ohta; Yoshihiro Hamada; Akira Kitamura; Noboru Tanabe; Hideharu Amano; Hironori Nakajo (PDPTA, 2007)

Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs. - Konosuke Watanabe; Tomohiro Otsuka; Junichiro Tsuchiya; Hiroaki Nishi; Junji Yamamoto; Noboru Tanabe; Tomohiro Kudoh; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2007)

An Enhancer of Memory and Network for Cluster and its Applications. - Noboru Tanabe; Hironori Nakajo (PDCAT, 2008)

Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network. - Noboru Tanabe; Hironori Nakajo (PVM/MPI, 2008)

Network Interface Architecture for Scalable Message Queue Processing. - Noboru Tanabe; Atsushi Ohta; Pulung Waskito; Hironori Nakajo (ICPADS, 2009)

The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing. - Noboru Tanabe; Manami Sasaki; Hironori Nakajo; Masami Takata; Kazuki Joe (PDPTA, 2009)

Acceleration for MPI derived datatypes using an enhancer of memory and network. - Noboru Tanabe; Hironori Nakajo (IPDPS Workshops, 2010)

An enhancer of memory and network for applications with large-capacity data and non-continuous data accessing. - Noboru Tanabe; Hirotaka Hakozaki; Hiroshi Ando; Yasunori Dohi; Zhengzhe Luo; Hironori Nakajo (J. Supercomput., 2010)

Scaleable Sparse Matrix-Vector Multiplication with Functional Memory and GPUs. - Noboru Tanabe; Yuuka Ogawa; Masami Takata; Kazuki Joe (PDP, 2011)

A memory accelerator with gather functions for bandwidth-bound irregular applications. - Noboru Tanabe; Boonyasitpichai Nuttapon; Hironori Nakajo; Yuka Ogawa; Junko Kogou; Masami Takata; Kazuki Joe (IA3@SC, 2011)

Character of Graph Analysis Workloads and Recommended Solutions on Future Parallel Systems. - Noboru Tanabe; Sonoko Tomimori; Masami Takata; Kazuki Joe (ICA3PP (1), 2013)

Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism. - Noboru Tanabe; Atsushi Ohta (IEICE Trans. Inf. Syst., 2013)

Exhaustive evaluation of memory-latency sensitivity on manycore processors with large cache. - Noboru Tanabe; Toshio Endo (HP3C, 2018)

Characterizing Memory-Latency Sensitivity of Sparse Matrix Kernels. - Noboru Tanabe; Toshio Endo (PDP, 2018)