Datapath Generator Based on Gate-Level Symbolic Layout. - Nobu Matsumoto; Yoko Watanabe; Kimiyoshi Usami; Yukio Sugeno; Hiroshi Hatada; Shojiro Mori (DAC, 1990)

Hierarchical symbolic design methodology for large-scale data paths. - Kimiyoshi Usami; Yukio Sugeno; Nobu Matsumoto; Shojiro Mori (IEEE J. Solid State Circuits, 1991)

A Compaction Method for Full Chip VLSI Layouts. - Joseph Dao; Nobu Matsumoto; Tsuneo Hamai; Chusei Ogawa; Shojiro Mori (DAC, 1993)

A New Verification Methodology for Complex Pipeline Behavior. - Kazuyoshi Kohno; Nobu Matsumoto (DAC, 2001)

A single-chip MPEG-2 codec based on customizable media microprocessor. - Shunichi Ishiwata; Tomoo Yamakage; Yoshiro Tsuboi; Takayoshi Shimazawa; Tomoko Kitazawa; Shuji Michinaka; Kunihiko Yahagi; Hideki Takeda; Akihiro Oue; Tomoya Kodama; Nobu Matsumoto; Takayuki Kamei; et al. (CICC, 2002)

Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture. - Atsushi Mizuno; Kazuyoshi Kohno; Ryuichiro Ohyama; Takahiro Tokuyoshi; Hironori Uetani; Hans Eichel; Takashi Miyamori; Nobu Matsumoto; Masataka Matsui (ICCD, 2002)

A single-chip MPEG-2 codec based on customizable media embedded processor. - Shunichi Ishiwata; Tomoo Yamakage; Yoshiro Tsuboi; Takayoshi Shimazawa; Tomoko Kitazawa; Shuji Michinaka; Kunihiko Yahagi; Hideki Takeda; Akihiro Oue; Tomoya Kodama; Nobu Matsumoto; Takayuki Kamei; et al. (IEEE J. Solid State Circuits, 2003)

Pack instruction generation for media pUsing multi-valued decision diagram. - Hiroaki Tanaka; Yoshinori Takeuchi; Keishi Sakanushi; Masaharu Imai; Yutaka Ota; Nobu Matsumoto; Masaki Nakagawa (CODES+ISSS, 2006)

Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram. - Hiroaki Tanaka; Yoshinori Takeuchi; Keishi Sakanushi; Masaharu Imai; Hiroki Tagawa; Yutaka Ota; Nobu Matsumoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Design and implementation of scalable, transparent threads for multi-core media processor. - Takeshi Kodaka; Shunsuke Sasaki; Takahiro Tokuyoshi; Ryuichiro Ohyama; Nobuhiro Nonogaki; Koji Kitayama; Tatsuya Mori; Yasuyuki Ueda; Hideho Arakida; Yuji Okuda; Toshiki Kizu; Yoshiro Tsuboi; et al. (DATE, 2009)

A new compilation technique for SIMD code generation across basic block boundaries. - Hiroaki Tanaka; Yutaka Ota; Nobu Matsumoto; Takuji Hieda; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2010)

A near-future prediction method for low power consumption on a many-core processor. - Takeshi Kodaka; Akira Takeda; Shunsuke Sasaki; Akira Yokosawa; Toshiki Kizu; Takahiro Tokuyoshi; Hui Xu; Toru Sano; Hiroyuki Usui; Jun Tanabe; Takashi Miyamori; Nobu Matsumoto (DATE, 2013)

Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR. - Ken Tanabe; Hiroshi Kubota; Akihide Sai; Nobu Matsumoto (COOL CHIPS, 2018)

A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique. - Kentaro Yoshioka; Hiroshi Kubota; Tomonori Fukushima; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Kaori Watanabe; Yoshinari Ojima; Katsuyuki Kimura; Sohichiroh Hosoda; Yutaka Ota; Tomohiro Koizumi; et al. (ISSCC, 2018)

A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC. - Kentaro Yoshioka; Hiroshi Kubota; Tomonori Fukushima; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Kaori Watanabe; Masatoshi Hirono; Yoshinari Ojima; Katsuyuki Kimura; Sohichiroh Hosoda; Yutaka Ota; et al. (IEEE J. Solid State Circuits, 2018)

Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel Resolution LiDAR. - Ken Tanabe; Hiroshi Kubota; Akihide Sai; Nobu Matsumoto (COOL CHIPS, 2019)

5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm2 Voltage/Time Dual-Data-Converter-Based AFE. - Satoshi Kondo; Hiroshi Kubota; Hisaaki Katagiri; Yutaka Ota; Masatoshi Hirono; Tuan Thanh Ta; Hidenori Okuni; Shinichi Ohtsuka; Yoshinari Ojima; Tomohiko Sugimoto; Hirotomo Ishii; Kentaro Yoshioka; et al. (ISSCC, 2020)

A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR. - Tuan Thanh Ta; Hiroshi Kubota; Koichi Kokubun; Toshiki Sugimoto; Masatoshi Hirono; Mitsuhiro Sengoku; Hisaaki Katagiri; Hidenori Okuni; Satoshi Kondo; Shinichi Ohtsuka; Honam Kwon; Keita Sasaki; et al. (VLSI Circuits, 2020)

An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm2 Voltage/Time Dual-Data-Converter-Based AFE. - Satoshi Kondo; Hiroshi Kubota; Hisaaki Katagiri; Yutaka Ota; Masatoshi Hirono; Tuan Thanh Ta; Hidenori Okuni; Shinichi Ohtsuka; Yoshinari Ojima; Tomohiko Sugimoto; Hirotomo Ishii; Kentaro Yoshioka; et al. (IEEE J. Solid State Circuits, 2020)