An outline font rendering processor with an embedded RISC CPU for high-speed hint processing. - Tetsuro Kawata; Kenichi Kawauchi; Nobuaki Miyakawa; Ichiro Kawazome; Hiromi Yasumatsu; Susumu Haga; Masaya Takenaka (IEEE J. Solid State Circuits, 1994)

Future system-on-silicon LSI chips. - Mitsumasa Koyanagi; Hiroyuki Kurino; Kang Wook Lee 002; Katsuyuki Sakuma; Nobuaki Miyakawa; Hikotaro Itani (IEEE Micro, 1998)

MOE: A Special-Purpose Parallel Computer for High-Speed, Large-Scale Molecular Orbital Calculation. - Koji Hashimoto; Hiroto Tomita; Koji Inoue; Katsuhiko Metsugi; Kazuaki J. Murakami; Shinjiro Inabata; So Yamada; Nobuaki Miyakawa; Hajime Takashima; Kunihiro Kitamura; Shigeru Obara; Takashi Amisaki; et al. (SC, 1999)

Development of MD Engine: High-speed accelerator with parallel processor design for molecular dynamics simulations. - Shinjiro Toyoda; Hiroh Miyagawa; Kunihiro Kitamura; Takashi Amisaki; Eiri Hashimoto; Hitoshi Ikeda; Akihiro Kusumi; Nobuaki Miyakawa (J. Comput. Chem., 1999)

A novel parallel algorithm for large-scale Fock matrix construction with small locally distributed memory architectures: RT parallel algorithm. - Hajime Takashima; So Yamada; Shigeru Obara; Kunihiro Kitamura; Shinjiro Inabata; Nobuaki Miyakawa; Kazutoshi Tanabe; Umpei Nagashima (J. Comput. Chem., 2002)

Stacking technology based on 8-inch wafers using direct connection between TSV and micro-bump. - Nobuaki Miyakawa; Eiri Hashimoto; Takanori Maebashi; Natsuo Nakamura; Yutaka Sacho; Shigeto Nakayama; Shinjiro Toyoda (CICC, 2008)

Multilayer stacking technology using wafer-to-wafer stacked method. - Nobuaki Miyakawa; Eiri Hashimoto; Takanori Maebashi; Natsuo Nakamura; Yutaka Sacho; Shigeto Nakayama; Shinjiro Toyoda (ACM J. Emerg. Technol. Comput. Syst., 2008)

A 3D prototyping chip based on a wafer-level stacking technology. - Nobuaki Miyakawa (ASP-DAC, 2009)

Keep-Out-Zone analysis for three-dimensional ICs. - Mostafa Said; Mohamed El-Sayed 011; Farhad Mehdipour; Nobuaki Miyakawa (VLSI-DAT, 2014)