A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design. - Kenichi Imamiya; Jun-ichi Miyamoto; Shigeru Atsumi; Nobuaki Ohtsuka; Yukinori Muroya; Toshiyuki Sako; Masao Higashino; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Hitoshi Araki; Yukio Kaneko; et al. (IEEE J. Solid State Circuits, 1990)

Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme. - Jun-ichi Miyamoto; Nobuaki Ohtsuka; Ken-ichi Imamiya; Naoto Tomita; Yumiko Iyama (ITC, 1991)

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique. - Naoto Tomita; Nobuaki Ohtsuka; Jun-ichi Miyamoto; Ken-ichi Imamiya; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Norihisa Arai; Yukio Kaneko; Eiji Sakagami; Kuniyoshi Yoshikawa; Sumio Tanaka (IEEE J. Solid State Circuits, 1991)