A design of Transimpedance Amplifier using OTA as a feedback resistor for patch-clamp measurement system. - Masahiro Kubo; Hiroki Yotsuda; Taro Kosaka; Nobuhiko Nakano (ISPACS, 2015)

Valiable frequency characteristics multi-channel on-chip patch-clamp system using 0.18 um CMOS technology. - Masahiro Kubo; Taro Kosaka; Takanori Miyawaki; Kota Ito; Nobuhiko Nakano (ISPACS, 2016)

Area-efficient cross-coupled charge pump for on-chip solar cell. - Yoshimasa Minami; Kazuma Igarashi; Takaya Sugiura; Nobuhiko Nakano (ISPACS, 2016)

Compensation Technique for Current-to-Voltage Converters for LSI Patch Clamp System Using High Resistive Feedback. - Hiroki Yotsuda; Retdian Agung Nicodimus; Masahiro Kubo; Taro Kosaka; Nobuhiko Nakano (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Low Noise Analog Front-end Design with an N-path Filter for Dry EEG Recording. - Takumi Deguchi; Ryoya Tanaka; Shohei Kawazoe; Ryuto Fukuoka; Nobuhiko Nakano (ISPACS, 2018)

A Delta-Sigma Modulator With Frequency Division Multiplexing for Multi-Channel EEG Acquisition Front-end. - Mikiyoshi Mikawa; Shohei Kawazoe; Ryuto Fukuoka; Nobuhiko Nakano (ICECS, 2019)

An On-Chip Self-Powered Non-Volatile One-Time-Programmable Memory System in Standard CMOS Technology. - Jorge Cañada; Yui Yoshida; Hiroki Miura; Nobuhiko Nakano (ICECS, 2020)

A Low-Power Multi-Frequency Chopper-Stabilized Readout with Time-Domain Delta-Sigma Modulator Suitable for Neural Recording. - Mikiyoshi Mikawa; Kenta Yagi; Kazuki Itakura; Leo Onuki; Nobuhiko Nakano (ICECS, 2020)

An On-Chip Scalable Low Power Consumption High-Voltage Driver Based on Standard CMOS Technology. - Jorge Cañada; Yui Yoshida; Hiroki Miura; Nobuhiko Nakano (ISOCC, 2020)

Speech Signal Processing Using Consonant-Vowel Location Detection. - Shusuke Nakazato; Nobuhiko Nakano (CANDAR (Workshops), 2021)

High-Temperature Operational Piezoresistive Pressure Sensor on Standard CMOS Process. - Takaya Sugiura; Hiroki Miura; Nobuhiko Nakano (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Germanium- and Silicon-Nanotransistor Designs by Electrical and Thermal Self-Consistent Analysis. - Takaya Sugiura; Shiun Yamakiri; Nobuhiko Nakano (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)