A 320 MFLOPS CMOS floating-point processing unit for superscalar processors. - Nobuhiro Ide; Hiroto Fukuhisa; Yoshihisa Kondo; Takeshi Yoshida; Masato Nagamatsu; Junji Mori; Itaru Yamazaki; Kiyoyi Ueno (IEEE J. Solid State Circuits, 1993)

30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit. - Gensoh Matsubara; Nobuhiro Ide; Haruyuki Tago; Seigo Suzuki; Nobuyuki Goto (IEEE Symposium on Computer Arithmetic, 1995)

A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit. - Gensoh Matsubara; Nobuhiro Ide (ASYNC, 1997)

A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder. - Masakazu Suzuoki; Ken Kutaragi; Toshiyuki Hiroi; Hidetaka Magoshi; Shin'ichi Okamoto; Masaaki Oka; Akio Ohba; Yasuyuki Yamamoto; Makoto Furuhashi; Masayoshi Tanaka; Teiji Yutaka; Toyoshi Okada; et al. (IEEE J. Solid State Circuits, 1999)

300MHz design methodology of VU for emotion synthesis. - Takayuki Kamei; Hideaki Takeda 002; Yukio Ootaguro; Takayoshi Shimazawa; Kazuhiko Tachibana; Shin'ichi Kawakami; Seiji Norimatsu; Fujio Ishihara; Toshinori Sato; Hiroaki Murakami; Nobuhiro Ide; Yukio Endo; et al. (ASP-DAC, 2000)

2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing. - Nobuhiro Ide; Masashi Hirano; Yukio Endo; Shin-ichi Yoshioka; Hiroaki Murakami; Atsushi Kunimatsu; Toshinori Sato; Takayuki Kamei; Toyoshi Okada; Masakazu Suzuoki (IEEE J. Solid State Circuits, 2000)

Vector Unit Architecture for Emotion Synthesis. - Atsushi Kunimatsu; Nobuhiro Ide; Toshinori Sato; Yukio Endo; Hiroaki Murakami; Takayuki Kamei; Masashi Hirano; Fujio Ishihara; Haruyuki Tago; Masaaki Oka; Akio Ohba; Teiji Yutaka; et al. (IEEE Micro, 2000)