An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. - Nobuho Hashimoto; Shinya Takamaeda-Yamazaki (FPL, 2021)

FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design. - Nobuho Hashimoto; Shinya Takamaeda-Yamazaki (FPT, 2022)

Efficient Matching Algorithms between Logs and Indicators for Automatic Incident Response System. - Satoshi Okada; Nobuho Hashimoto; Takuho Mitsunaga (J. Inf. Process., 2023)