Parallel neural network simulation machine: Neuman. - Nobuki Kajihara; Satoshi Matsushita; Toshiyuki Nakata 001; Nobuhiko Koike (Neural Networks, 1988)

MAN-YO: Mixed level parallel logic simulation engine. - Nobuhiko Koike; Toshiyuki Nakata 001; Nobuki Kajihara (Syst. Comput. Jpn., 1989)

SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method. - Tsukasa Yamauchi; Shogo Nakaya; Nobuki Kajihara (FCCM, 1996)

SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method. - Tsukasa Yamauchi; Shogo Nakaya; Nobuki Kajihara (Parcella, 1996)

Evolvable Hardware Chip for High Precision Printer Image Compression. - Hidenori Sakanashi; Mehrdad Salami; Masaya Iwata; Shogo Nakaya; Tsukasa Yamauchi; Takeshi Inuo; Nobuki Kajihara; Tetsuya Higuchi (AAAI/IAAI, 1998)

A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. - Isamu Kajitani; Tsutomu Hoshino; Daisuke Nishikawa; Hiroshi Yokoi; Shogo Nakaya; Tsukasa Yamauchi; Takeshi Inuo; Nobuki Kajihara; Masaya Iwata; Didier Keymeulen; Tetsuya Higuchi (ICES, 1998)

An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller. - Isamu Kajitani; Tsutomu Hoshino; Nobuki Kajihara; Masaya Iwata; Tetsuya Higuchi (AAAI/IAAI, 1999)

Evolvable Hardware Chips for Neural Network Applications. - Isamu Kajitani; Masahiro Murakawa; Nobuki Kajihara; Masaya Iwata; Hidenori Sakanashi; Tetsuya Higuchi (ICANNGA, 1999)

Evolvable Hardware Chips for Industrial Applications. - Tetsuya Higuchi; Nobuki Kajihara (Commun. ACM, 1999)

The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing. - Masahiro Murakawa; Shuji Yoshizawa; Isamu Kajitani; Xin Yao 001; Nobuki Kajihara; Masaya Iwata; Tetsuya Higuchi (IEEE Trans. Computers, 1999)

Real-world applications of analog and digital evolvable hardware . - Tetsuya Higuchi; Masaya Iwata; Didier Keymeulen; Hidenori Sakanashi; Masahiro Murakawa; Isamu Kajitani; Eiichi Takahashi; Kenji Toda; Mehrdad Salami; Nobuki Kajihara; Nobuyuki Otsu (IEEE Trans. Evol. Comput., 1999)

Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. - Tsukasa Yamauchi; Shogo Nakaya; Takeshi Inuo; Nobuki Kajihara (FCCM, 2000)

Arithmetic Operation Oriented Reconfigurable Chip: RHW. - Tsukasa Yamauchi; Shogo Nakaya; Takeshi Inuo; Nobuki Kajihara (FPL, 2001)

Implementation of a Gate-Level Evolvable Hardware Chip. - Masaya Iwata; Isamu Kajitani; Yong Liu 012; Nobuki Kajihara; Tetsuya Higuchi (ICES, 2001)

FPGA Implementation for Large Scale Reservoir Computing based on Chaotic Boltzmann Machine. - Shigeki Matsumoto; Yuki Ichikawa; Nobuki Kajihara; Hakaru Tamukoh (ISCAS, 2024)