Characteristics of the multiple-input DC-DC converter. - Hirofumi Matsuo; Wenzhong Lin; Fujio Kurokawa; Tetsuro Shigemizu; Nobuya Watanabe (IEEE Trans. Ind. Electron., 2004)

Optically Reconfigurable Gate Array VLSI That Can Support a Perfect Parallel Configuration. - Sae Goto; Minoru Watanabe; Nobuya Watanabe (APCCAS, 2022)

Convolutional neural network implementations using Vitis AI. - Akihiko Ushiroyama; Minoru Watanabe; Nobuya Watanabe; Akira Nagoya (CCWC, 2022)

Total Dose Tolerance Analysis of an Optically Reconfigurable Gate Array VLSI. - Kaho Yamada; Takeshi Okazaki; Minoru Watanabe; Nobuya Watanabe (ICECS 2022, 2022)

Video Indexing for Live Nature Camera on Digital Earth. - Hiroki Mimura; Masaya Tahara; Kosuke Takano; Nobuya Watanabe; Kin Fun Li (AINA (3), 2023)

Total-Ionizing-Dose Tolerance Analysis of a Radiation-Hardened Image Sensor. - Daisuke Bamba; Minoru Watanabe; Nobuya Watanabe (ICCE, 2023)

Multi-context-scrubbing operation for a 1-bit counter circuit. - Kakeru Ando; Minoru Watanabe; Nobuya Watanabe (NEWCAS, 2023)

An optically reconfigurable gate array VLSI driven by an unstabilized power supply unit. - Masashi Tsujino; Minoru Watanabe; Nobuya Watanabe (SOCC, 2023)

A Classification Method of Image Feature Using Neural Metric Learning for Natural Environment Video. - Yukito Seo; Rafly Arief Kanza; Nobuya Watanabe; Kin Fun Li; Kosuke Takano (AINA (6), 2024)

Voltage Range Evaluation of An Optically Reconfigurable Gate Array VLSI. - Yuki Shimamura; Minoru Watanabe; Nobuya Watanabe (ASAP, 2024)

Parallel configuration experiment for a radiation-hardened optically reconfigurable gate array with a holographic polymer-dispersed liquid crystal memory. - Sae Goto; Minoru Watanabe; Akifumi Ogiwara; Nobuya Watanabe (ICCE, 2024)

Remote monitoring system for optically reconfigurable gate arrays in radiation environments. - Utsuki Sekioka; Minoru Watanabe; Nobuya Watanabe (ICCE, 2024)

Wafer-scale VLSI realization using programmable architecture. - Atsushi Takata; Minoru Watanabe; Nobuya Watanabe (ICCE, 2024)

Application design system for high-speed dynamically reconfigurable gate arrays. - Nobuya Watanabe; Ryoya Ishitani; Minoru Watanabe (ICCE, 2024)

Ring oscillator based clock generation for a radiation-hardened optically reconfigurable gate array VLSI. - Shintaro Takatsuki; Minoru Watanabe; Nobuya Watanabe (SOCC, 2024)

Reliability Calculation for Captured Images in Mobile Observation for Natural Environments. - Yukito Seo; Kosuke Takano; Nobuya Watanabe; Kin Fun Li (EIDWT, 2025)

Implementation of Mono Instruction Set Computer with Small Register Files. - Soma Imai; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Development of a Radiation-Hardened JTAG Interface for Optically Reconfigurable Gate Arrays. - Naoki Nagamine; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Demonstration of a Clock Distribution Method using Switching Matrices and a Two-Phase Clock Signal on an FPGA. - Ayumu Ogura; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Radiation Degradation Evaluation of the Dynamic Configuration Circuit on An Optically Reconfigurable Gate Array VLSI. - Seiji Ohashi; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Radiation-Hardened Triple Modular Redundant Serial Communication System Using Triple Communication Lines. - Utsuki Sekioka; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Realization of Wafer-Scale VLSI Using Optical Configuration Architecture. - Atsushi Takata; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Triple Modular Redundancy Logic Design from High-Level Hardware Description. - Nobuya Watanabe; Minoru Watanabe (ICCE, 2025)