MIXS: A mixed level simulator for large digital system logic verification. - Tohru Sasaki; Akihiko Yamada; Shunichi Kato; Terufumi Nakazawa; Kyoji Tomita; Nobuyoshi Nomizu (DAC, 1980)

Logic Design Verification Using Automated Test Generation. - Tohru Sasaki; Shunichi Kato; Nobuyoshi Nomizu; Hidetoshi Tanaka (ITC, 1984)

HAL II: a mixed level hardware logic simulation system. - Shigeru Takasaki; Tohru Sasaki; Nobuyoshi Nomizu; Hiroshi Ishikura; Nobuhiko Koike (DAC, 1986)

Block-Level Hardware Logic Simulation Machine. - Shigeru Takasaki; Tohru Sasaki; Nobuyoshi Nomizu; Nobuhiko Koike; Kenji Ohmori (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

A Framework Environment for Logic Design Support System. - Kaname Kuroki; Nobuyoshi Nomizu; Shigenobu Suzuki; Kazutoshi Takahashi (ICCAD, 1990)

HAL III: function level hardware logic simulation. - Shigeru Takasaki; Nobuyoshi Nomizu; Yoshihiro Hirabayashi; Hiroshi Ishikura; Masahiro Kurashita; Nobuhiko Koike; Toshiyuki Nakata 001 (ICCD, 1990)

Timing Optimization on Mapped Circuits. - Ko Yoshikawa; Hiroshi Ichiryu; Hisato Tanishita; Shigenobu Suzuki; Nobuyoshi Nomizu; Akira Kondoh (DAC, 1991)