High-level power analysis for on-chip networks. - Noel Eisley; Li-Shiuan Peh (CASES, 2004)

High-level power analysis for multi-core chips. - Noel Eisley; Vassos Soteriou; Li-Shiuan Peh (CASES, 2006)

Polaris: A System-Level Roadmap for On-Chip Interconnection Networks. - Vassos Soteriou; Noel Eisley; Hangsheng Wang; Bin Li 018; Li-Shiuan Peh (ICCD, 2006)

In-network cache coherence. - Noel Eisley; Li-Shiuan Peh; Li Shang (IEEE Comput. Archit. Lett., 2006)

Software-directed power-aware interconnection networks. - Vassos Soteriou; Noel Eisley; Li-Shiuan Peh (ACM Trans. Archit. Code Optim., 2007)

Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks. - Vassos Soteriou; Noel Eisley; Hangsheng Wang; Bin Li 018; Li-Shiuan Peh (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Leveraging on-chip networks for data cache migration in chip multiprocessors. - Noel Eisley; Li-Shiuan Peh; Li Shang (PACT, 2008)

The IBM Blue Gene/Q interconnection network and message unit. - Dong Chen 005; Noel Eisley; Philip Heidelberger; Robert M. Senger; Yutaka Sugawara; Sameer Kumar 001; Valentina Salapura; David L. Satterfield; Burkhard D. Steinmacher-Burow; Jeffrey J. Parker (SC, 2011)

Looking under the hood of the IBM blue gene/Q network. - Dong Chen 005; Noel Eisley; Philip Heidelberger; Sameer Kumar 001; Amith R. Mamidala; Fabrizio Petrini; Robert M. Senger; Yutaka Sugawara; Robert Walkup; Burkhard D. Steinmacher-Burow; Anamitra R. Choudhury; Yogish Sabharwal; et al. (SC, 2012)

The IBM Blue Gene/Q Interconnection Fabric. - Dong Chen 005; Noel Eisley; Philip Heidelberger; Robert M. Senger; Yutaka Sugawara; Sameer Kumar 001; Valentina Salapura; David L. Satterfield; Burkhard D. Steinmacher-Burow; Jeffrey J. Parker (IEEE Micro, 2012)