Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. - Satyamurthy Pullela; Noel Menezes; Lawrence T. Pillage (DAC, 1993)

A Gate-Delay Model for high-Speed CMOS Circuits. - Florentin Dartu; Noel Menezes; Jessica Qian; Lawrence T. Pillage (DAC, 1994)

Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. - Ronn B. Brashear; Noel Menezes; Chanhee Oh; Lawrence T. Pillage; M. Ray Mercer (EDAC-ETC-EUROASIC, 1994)

RC interconnect synthesis-a moment fitting approach. - Noel Menezes; Satyamurthy Pullela; Florentin Dartu; Lawrence T. Pillage (ICCAD, 1994)

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. - Noel Menezes; Satyamurthy Pullela; Lawrence T. Pileggi (DAC, 1995)

Performance computation for precharacterized CMOS gates with RC loads. - Florentin Dartu; Noel Menezes; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Post-processing of clock trees via wiresizing and buffering for robust design. - Satyamurthy Pullela; Noel Menezes; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Clustering and Load Balancing for Buffered Clock Tree Synthesis. - Ashih D. Mehta; Yao-Ping Chen; Noel Menezes; D. F. Wong 001; Lawrence T. Pileggi (ICCD, 1997)

A sequential quadratic programming approach to concurrent gate and wire sizing. - Noel Menezes; Ross Baldick; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. - Satyamurthy Pullela; Noel Menezes; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. - Chung-Ping Chen; Noel Menezes (DAC, 1999)

Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. - Noel Menezes; Chung-Ping Chen (VLSI Design, 1999)

Optimization and Analysis Techniques for the Deep Submicron Regime. - Noel Menezes; Sachin S. Sapatnekar (VLSI Design, 2001)

The scaling challenge: can correct-by-construction design help? - Prashant Saxena; Noel Menezes; Pasquale Cocchini; Desmond Kirkpatrick (ISPD, 2003)

Statistical timing analysis based on a timing yield model. - Farid N. Najm; Noel Menezes (DAC, 2004)

Repeater scaling and its impact on CAD. - Prashant Saxena; Noel Menezes; Pasquale Cocchini; Desmond Kirkpatrick (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Statistical static timing analysis: how simple can we get? - Chirayu S. Amin; Noel Menezes; Kip Killpack; Florentin Dartu; Umakanta Choudhury; Nagib Hakim; Yehea I. Ismail (DAC, 2005)

Variability modeling and variability-aware design in deep submicron integrated circuits. - Florentin Dartu; Anirudh Devgan; Noel Menezes (ACM Great Lakes Symposium on VLSI, 2005)

A multi-port current source model for multiple-input switching effects in CMOS library cells. - Chirayu S. Amin; Chandramouli V. Kashyap; Noel Menezes; Kip Killpack; Eli Chiprout (DAC, 2006)

Comparative Analysis of Conventional and Statistical Design Techniques. - Steven M. Burns; Mahesh Ketkar; Noel Menezes; Keith A. Bowman; James W. Tschanz; Vivek De (DAC, 2007)

A nonlinear cell macromodel for digital applications. - Chandramouli V. Kashyap; Chirayu S. Amin; Noel Menezes; Eli Chiprout (ICCAD, 2007)

The good, the bad, and the statistical. - Noel Menezes (ISPD, 2007)

A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. - Farid N. Najm; Noel Menezes; Imad A. Ferzli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A "true" electrical cell model for timing, noise, and power grid verification. - Noel Menezes; Chandramouli V. Kashyap; Chirayu S. Amin (DAC, 2008)

Session details: Keynote. - Noel Menezes (ISPD, 2019)