A low-error, memory-based fast binary antilogarithmic converter. - L. Guna Sekhar Sai Harsha; Bhaskara Rao Jammu 001; Visweswara Rao Samoju; Sreehari Veeramachaneni; Noor Mohammad S. (Int. J. Circuit Theory Appl., 2021)

A Low Error, Hardware Efficient Logarithmic Multiplier. - L. Guna Sekhar Sai Harsha; Bhaskara Rao Jammu 001; Nalini Bodasingi; Sreehari Veeramachaneni; Noor Mohammad S. (Circuits Syst. Signal Process., 2022)

Hardware efficient circuit for low error logarithmic converter. - Bhaskara Rao Jammu 001; L. Guna Sekhar Sai Harsha; Nalini Bodasingi; Sreehari Veeramachaneni; Noor Mohammad S. (J. Comput. Methods Sci. Eng., 2022)