Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories. - Nor Zaidi Haron; Said Hamdioui (DFT, 2009)

Residue-based code for reliable hybrid memories. - Nor Zaidi Haron; Said Hamdioui (NANOARCH, 2009)

Emerging non-CMOS nanoelectronic devices - What are they?. - Nor Zaidi Haron; Said Hamdioui; Sorin Cotofana (NEMS, 2009)

High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories. - Nor Zaidi Haron; Said Hamdioui (DFT, 2010)

ECC design for fault-tolerant crossbar memories: A case study. - Nor Zaidi Haron; Said Hamdioui; Zaiyan Ahyadi (IDT, 2010)

On Defect Oriented Testing for Hybrid CMOS/Memristor Memory. - Nor Zaidi Haron; Said Hamdioui (Asian Test Symposium, 2011)

Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories. - Nor Zaidi Haron; Said Hamdioui (DATE, 2011)

NBTI Monitoring and Design for Reliability in Nanoscale Circuits. - Seyab Khan; Nor Zaidi Haron; Said Hamdioui; Francky Catthoor (DFT, 2011)

Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories. - Nor Zaidi Haron; Said Hamdioui (ACM J. Emerg. Technol. Comput. Syst., 2011)

DfT schemes for resistive open defects in RRAMs. - Nor Zaidi Haron; Said Hamdioui (DATE, 2012)

Testing Open Defects in Memristor-Based Memories. - Said Hamdioui; Mottaqiallah Taouil; Nor Zaidi Haron (IEEE Trans. Computers, 2015)