Logic soft errors in sub-65nm technologies design and CAD challenges. - Subhasish Mitra; Tanay Karnik; Norbert Seifert; Ming Zhang (DAC, 2005)

Node sensitivity analysis for soft errors in CMOS logic. - Balkaran S. Gill; Christos A. Papachristou; Francis G. Wolff; Norbert Seifert (ITC, 2005)

Logic soft errors: a major barrier to robust platform design. - Subhasish Mitra; Ming Zhang 017; T. M. Mak; Norbert Seifert; Victor Zia; Kee Sup Kim (ITC, 2005)

Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim. - Subhasish Mitra; Norbert Seifert; Ming Zhang 017; Quan Shi; Kee Sup Kim (Computer, 2005)

Extending Moore's Law into the next Decade - the SER Challenge. - Norbert Seifert (IOLTS, 2006)

Combinational Logic Soft Error Correction. - Subhasish Mitra; Ming Zhang 017; Saad Waqas; Norbert Seifert; Balkaran S. Gill; Kee Sup Kim (ITC, 2006)

Soft Error Resilient System Design through Error Correction. - Subhasish Mitra; Ming Zhang 017; Norbert Seifert; T. M. Mak; Kee Sup Kim (VLSI-SoC (Selected Papers), 2006)

Sequential Element Design With Built-In Soft Error Resilience. - Ming Zhang 017; Subhasish Mitra; T. M. Mak; Norbert Seifert; Nicholas J. Wang; Quan Shi; Kee Sup Kim; Naresh R. Shanbhag; Sanjay J. Patel (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Soft Errors: Technology Trends, System Effects, and Protection Techniques. - Subhasish Mitra; Pia N. Sanda; Norbert Seifert (IOLTS, 2007)

Design for Resilience to Soft Errors and Variations. - Ming Zhang 017; T. M. Mak; James W. Tschanz; Kee Sup Kim; Norbert Seifert; Davia Lu (IOLTS, 2007)

Special Session 1: Radiation Hardening Techniques. - Norbert Seifert (IOLTS, 2008)

Soft Error Rates of Hardened Sequentials utilizing Local Redundancy. - Norbert Seifert (IOLTS, 2008)

Explaining cache SER anomaly using DUE AVF measurement. - Arijit Biswas; Charles Recchia; Shubhendu S. Mukherjee; Vinod Ambrose; Leo Chan; Aamer Jaleel; Athanasios E. Papathanasiou; Mike Plaster; Norbert Seifert (HPCA, 2010)

Radiation-induced Soft Errors: A Chip-level Modeling Perspective. - Norbert Seifert (Found. Trends Electron. Des. Autom., 2010)

Timing vulnerability factors of sequential elements in modern microprocessors. - Arkady Bramnik; Andrei Sherban; Norbert Seifert (IOLTS, 2013)

Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets. - Norbert Seifert; Shah M. Jahinuzzaman; Jyothi Velamala; Nikunj Patel (IRPS, 2015)

MBU-Calc: A compact model for Multi-Bit Upset (MBU) SER estimation. - Wei Wu; Norbert Seifert (IRPS, 2015)

On the Correlation of Laser-induced and High-Energy Proton Beam-induced Single Event Latchup. - Bahar Ajdari; Samwel Sekwao; Ricardo Ascázubi; Adam Neale; Norbert Seifert (IRPS, 2020)

A Reliability Overview of Intel's 10+ Logic Technology. - Rohit Grover; Tony Acosta; C. AnDyke; Emre Armagan; C. Auth; Sunny Chugh; K. Downes; M. Hattendorf; N. Jack; S. Joshi; R. Kasim; Gerald S. Leatherman; et al. (IRPS, 2020)