A 64-Mb DRAM with meshed power line. - Toshio Yamada; Yoshiro Nakata; Junko Hasegawa; Noriaki Amano; Akinori Shibayama; Masaru Sasago; Naoto Matsuo; Toshiki Yabu; Susumu Matsumoto; Shozo Okada; Michihiro Inoue (IEEE J. Solid State Circuits, 1991)