Numerical simulation of neuronal population coding: influences of noise and tuning width on the coding error. - Shoji Tanaka; Noriaki Nakayama (Biol. Cybern., 1995)

Correlation method of circuit-performance and technology fluctuations for improved design reliability. - D. Miyawaki; Shizunori Matsumoto; Hans Jürgen Mattausch; S. Ooshiro; Masami Suetake; Mitiko Miura-Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (ASP-DAC, 2001)

Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability. - Shizunori Matsumoto; Hans Jürgen Mattausch; S. Ooshiro; Y. Tatsumi; Mitiko Miura-Mattausch; Shigetaka Kumashiro; Terufumi Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (CICC, 2001)

Circuit Simulation Models for Coming MOSFET Generations. - Mitiko Miura-Mattausch; Hiroaki Ueno; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

On discrete random dopant modeling in drift-diffusion simulations: physical meaning of 'atomistic' dopants. - Nobuyuki Sano; Kazuya Matsuzawa; Mikio Mukai; Noriaki Nakayama (Microelectron. Reliab., 2002)

Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design. - Kazuya Hisamitsu; Hiroaki Ueno; Masayasu Tanaka; Daisuke Kitamaru; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (ASP-DAC, 2003)

1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation. - Shizunori Matsumoto; Hiroaki Ueno; Satoshi Hosokawa; Toshihiko Kitamura; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Electron., 2005)

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. - Dondee Navarro; Takeshi Mizoguchi; Masami Suetake; Kazuya Hisamitsu; Hiroaki Ueno; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Electron., 2005)

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. - Takashi Sato 001; Takumi Uezono; Shiho Hagiwara; Kenichi Okada 001; Shuhei Amakawa; Noriaki Nakayama; Kazuya Masu (ISQED, 2007)

Determination of optimal polynomial regression function to decompose on-die systematic and random variations. - Takashi Sato 001; Hiroyuki Ueyama; Noriaki Nakayama; Kazuya Masu (ASP-DAC, 2008)

Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. - Masanori Imai; Takashi Sato 001; Noriaki Nakayama; Kazuya Masu (DAC, 2008)

An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis. - Masanori Imai; Takashi Sato 001; Noriaki Nakayama; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. - Kenta Yamada; Takashi Sato 001; Shuhei Amakawa; Noriaki Nakayama; Kazuya Masu; Shigetaka Kumashiro (IEICE Trans. Electron., 2008)

Physical design challenges to nano-CMOS circuits. - Kazuya Masu; Noboru Ishihara; Noriaki Nakayama; Takashi Sato 001; Shuhei Amakawa (IEICE Electron. Express, 2009)

Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors. - Takashi Sato 001; Hiroyuki Ueyama; Noriaki Nakayama; Kazuya Masu (IEEE J. Solid State Circuits, 2009)

Decomposition of drain-current variation into gain-factor and threshold voltage variations. - Takashi Sato 001; Takumi Uezono; Noriaki Nakayama; Kazuya Masu (ISCAS, 2010)