A Pulse Width controlled PLL and its automated design flow. - Norihito Tohge; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2013)

A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. - Tetsuya Iizuka; Norihito Tohge; Satoshi Miura; Yoshimichi Murakami; Toru Nakura; Kunihiro Asada (ESSCIRC, 2016)