GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's. - Norio Higashisaka; M. Shimada; Akira Ohta; Kenji Hosogi; Y. Tobita; Yasuo Mitsui (IEEE J. Solid State Circuits, 1994)

A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure. - Akira Ohta; Norio Higashisaka; Tetsuya Heima; Takayuki Hisaka; Hirofumi Nakano; Ryuji Ohmura; Tadashi Takagi; Noriyuki Tanino (IEEE J. Solid State Circuits, 1999)