A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. - Koichi Takeda 001; Yoshiharu Aimoto; Noritsugu Nakamura; Hideo Toyoshima; Takahiro Iwasaki; Kenji Noda; Koujirou Matsui; Shinya Itoh; Sadaaki Masuoka; Tadahiko Horiuchi; Atsushi Nakagawa; Kenju Shimogawa; et al. (IEEE J. Solid State Circuits, 2000)

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. - Kenji Noda; Koichi Takeda 001; Koujirou Matsui; Shinya Ito; Sadaaki Masuoka; Hideaki Kawamoto; Nobuyuki Ikezawa; Yoshiharu Aimoto; Noritsugu Nakamura; Takahiro Iwasaki; Hideo Toyoshima; Tadahiko Horiuchi (IEEE J. Solid State Circuits, 2001)

High-level synthesis challenges and solutions for a dynamically reconfigurable processor. - Takao Toi; Noritsugu Nakamura; Yoshinosuke Kato; Toru Awashima; Kazutoshi Wakabayashi; Li Jing (ICCAD, 2006)

High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor. - Takao Toi; Noritsugu Nakamura; Yoshinosuke Kato; Toru Awashima; Kazutoshi Wakabayashi (Inf. Media Technol., 2010)

Optimizing time and space multiplexed computation in a dynamically reconfigurable processor. - Takao Toi; Noritsugu Nakamura; Taro Fujii; Toshiro Kitaoka; Katsumi Togawa; Koichiro Furuta; Toru Awashima (FPT, 2013)

Constructing a Human-like agent for the Werewolf Game using a psychological model based multiple perspectives. - Noritsugu Nakamura; Michimasa Inaba; Kenichi Takahashi; Fujio Toriumi; Hirotaka Osawa; Daisuke Katagami; Kousuke Shinoda (SSCI, 2016)

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. - Taro Fujii; Takao Toi; Teruhito Tanaka; Katsumi Togawa; Toshiro Kitaoka; Kengo Nishino; Noritsugu Nakamura; Hiroki Nakahara; Masato Motomura (VLSI Circuits, 2018)