Automatic Incorporation of On-Chip Testability Circuits. - Noriyuki Ito (DAC, 1990)

A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor. - Noriyuki Ito; Hiroaki Komatsu; Yoshiyasu Tanamura; Ryoichi Yamashita; Hiroyuki Sugiyama; Yaroku Sugiyama; Hirofumi Hamamura (ICCD, 2003)

Detection of multiple transitions in delay fault test of SPARC64 microprocessor. - Daisuke Maruyama; Akira Kanuma; Takashi Mochiyama; Hiroaki Komatsu; Yaroku Sugiyama; Noriyuki Ito (ICCAD, 2004)

Delay defect screening for a 2.16GHz SPARC64 microprocessor. - Noriyuki Ito; Akira Kanuma; Daisuke Maruyama; Hitoshi Yamanaka; Tsuyoshi Mochizuki; Osamu Sugawara; Chihiro Endoh; Masahiro Yanagida; Takeshi Kono; Yutaka Isoda; Kazunobu Adachi; Takahisa Hiraide; et al. (ASP-DAC, 2006)

Diagonal routing in high performance microprocessor design. - Noriyuki Ito; Hideaki Katagiri; Ryoichi Yamashita; Hiroshi Ikeda; Hiroyuki Sugiyama; Hiroaki Komatsu; Yoshiyasu Tanamura; Akihiro Yoshitake; Kazuhiro Nonomura; Kinya Ishizaka; Hiroaki Adachi; Yutaka Mori; et al. (ASP-DAC, 2006)

Design Methodology for 2.4GHz Dual-Core Microprocessor. - Noriyuki Ito; Hiroaki Komatsu; Akira Kanuma; Akihiro Yoshitake; Yoshiyasu Tanamura; Hiroyuki Sugiyama; Ryoichi Yamashita; Ken-ichi Nabeya; Hironobu Yoshino; Hitoshi Yamanaka; Masahiro Yanagida; Yoshitomo Ozeki; et al. (ASP-DAC, 2007)

Fast power network analysis with multiple clock domains. - Wanping Zhang; Ling Zhang; Rui Shi 003; He Peng; Zhi Zhu; Lew Chua-Eoan; Rajeev Murgai; Toshiyuki Shibuya; Noriyuki Ito; Chung-Kuan Cheng (ICCD, 2007)

Efficient Power Network Analysis Considering Multidomain Clock Gating. - Wanping Zhang; Wenjian Yu; Xiang Hu; Ling Zhang; Rui Shi 003; He Peng; Zhi Zhu; Lew Chua-Eoan; Rajeev Murgai; Toshiyuki Shibuya; Noriyuki Ito; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)