Practical methodology of post-layout gate sizing for 15% more power saving. - Noriyuki Miura; Naoki Kato; Tadahiro Kuroda (ASP-DAC, 2004)

Cross talk countermeasures in inductive inter-chip wireless superconnect. - Noriyuki Miura; Daisuke Mizoguchi; Takayasu Sakurai; Tadahiro Kuroda (CICC, 2004)

Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. - Noriyuki Miura; Daisuke Mizoguchi; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2006)

Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication. - Amit Kumar 022; Noriyuki Miura; Muhammad Muqsith; Tadahiro Kuroda (VLSI Design, 2006)

A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. - Daisuke Mizoguchi; Noriyuki Miura; Takayasu Sakurai; Tadahiro Kuroda (IEICE Trans. Electron., 2006)

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2006)

A 1Tb/s 3W Inductive-Coupling Transceiver Chip. - Noriyuki Miura; Tadahiro Kuroda (ASP-DAC, 2007)

Wideband Inductive-coupling Interface for High-performance Portable System. - Hiroki Ishikuro; Noriyuki Miura; Tadahiro Kuroda (CICC, 2007)

A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. - Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2007)

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. - Kiichi Niitsu; Noriyuki Miura; Mari Inoue; Yoshihiro Nakagawa; Masamoto Tago; Masayuki Mizuno; Takayasu Sakurai; Tadahiro Kuroda (IEICE Trans. Electron., 2007)

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. - Noriyuki Miura; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

An 11Gb/s Inductive-Coupling Link with Burst Transmission. - Noriyuki Miura; Yoshinori Kohama; Yasufumi Sugimori; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2008)

Constant Magnetic Field Scaling in Inductive-Coupling Data Link. - Daisuke Mizoguchi; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEICE Trans. Electron., 2008)

A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. - Noriyuki Miura; Hiroki Ishikuro; Kiichi Niitsu; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2008)

A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array. - Yoichi Yoshida; Noriyuki Miura; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2008)

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. - Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2009)

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. - Shotaro Saito; Yoshinori Kohama; Yasufumi Sugimori; Yohei Hasegawa; Hiroki Matsutani; Toru Sano; Kazutaka Kasuga; Yoichi Yoshida; Kiichi Niitsu; Noriyuki Miura; Tadahiro Kuroda; Hideharu Amano (FPL, 2009)

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. - Yasufumi Sugimori; Yoshinori Kohama; Mitsuko Saito; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2009)

A High-Speed Inductive-Coupling Link With Burst Transmission. - Noriyuki Miura; Yoshinori Kohama; Yasufumi Sugimori; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2009)

An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. - Noriyuki Miura; Kazutaka Kasuga; Mitsuko Saito; Tadahiro Kuroda (ISSCC, 2010)

A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking. - Mitsuko Saito; Noriyuki Miura; Tadahiro Kuroda (ISSCC, 2010)

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. - Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2010)

47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. - Mitsuko Saito; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking. - Noriyuki Miura; Yasuhiro Take; Mitsuko Saito; Yoichi Yoshida; Tadahiro Kuroda (ISSCC, 2011)

6W/25mm2 inductive power transfer for non-contact wafer-level testing. - Andrzej Radecki; Hayun Chung; Yoichi Yoshida; Noriyuki Miura; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2011)

A 12Gb/s non-contact interface with coupled transmission lines. - Tsutomu Takeya; Lan Nan; Shinya Nakano; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2011)

A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme. - Noriyuki Miura; Tsunaaki Shidei; Yuxiang Yuan; Shusuke Kawai; Keita Takatsu; Yuji Kiyota; Yuichi Asano; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2011)

A 30 Gb/s/Link 2.2 Tb/s/mm 2 Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface. - Yasuhiro Take; Noriyuki Miura; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2011)

Simultaneous data and power transmission using nested clover coils. - Yasuhiro Take; Hayun Chung; Noriyuki Miura; Tadahiro Kuroda (ASP-DAC, 2012)

A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. - Atsutake Kosuge; Wataru Mizuhara; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2012)

A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. - Yasuhisa Shimazaki; Noriyuki Miura; Tadahiro Kuroda (COOL Chips, 2012)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. - Yusuke Koizumi; Hideharu Amano; Hiroki Matsutani; Noriyuki Miura; Tadahiro Kuroda; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPT, 2012)

A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. - Won-Joo Yun; Shinya Nakano; Wataru Mizuhara; Atsutake Kosuge; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2012)

A 1 TB/s 1 pJ/b 6.4 mm2/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM. - Noriyuki Miura; Mitsuko Saito; Tadahiro Kuroda (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

6 W/25 mm2 Wireless Power Transmission for Non-contact Wafer-Level Testing. - Andrzej Radecki; Hayun Chung; Yoichi Yoshida; Noriyuki Miura; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda (IEICE Trans. Electron., 2012)

A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. - Hayun Chung; Andrzej Radecki; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. - Andrzej Radecki; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. - Andrzej Radecki; Yuxiang Yuan; Noriyuki Miura; Iori Aikawa; Yasuhiro Take; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2012)

A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. - Kiichi Niitsu; Shusuke Kawai; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator. - Naoya Azuma; Shunsuke Shimazaki; Noriyuki Miura; Makoto Nagata; Tomomitsu Kitamura; Satoru Takahashi; Motoki Murakami; Kazuaki Hori; Atsushi Nakamura; Kenta Tsukamoto; Mizuki Iwanami; Eiji Hankui; et al. (EMC Compo, 2013)

Immunity evaluation of inverter chains against RF power on power delivery network. - Kumpei Yoshikawa; Yuji Harada; Noriyuki Miura; Noriaki Takeda; Yoshiyuki Saito; Makoto Nagata (EMC Compo, 2013)

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. - Yusuke Koizumi; Noriyuki Miura; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPL, 2013)

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. - Noriyuki Miura; Yusuke Koizumi; Eiichi Sasaki; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (Hot Chips Symposium, 2013)

A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×. - Noriyuki Miura; Mitsuko Saito; Masao Taguchi; Tadahiro Kuroda (ISSCC, 2013)

A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. - Wataru Mizuhara; Tsunaaki Shidei; Atsutake Kosuge; Tsutomu Takeya; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2013)

3D clock distribution using vertically/horizontally-coupled resonators. - Yasuhiro Take; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2013)

A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. - Tsutomu Takeya; Lan Nan; Shinya Nakano; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2013)

A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. - Noriyuki Miura; Yusuke Koizumi; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (IEEE Micro, 2013)

An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. - Noriyuki Miura; Daisuke Fujimoto; Rie Korenaga; Kohei Matsuda; Makoto Nagata (A-SSCC, 2014)

On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. - Makoto Nagata; Daisuke Fujimoto; Noriyuki Miura (ATS, 2014)

Side-channel leakage on silicon substrate of CMOS cryptographic chip. - Daisuke Fujimoto; Daichi Tanaka; Noriyuki Miura; Makoto Nagata; Yu-ichi Hayashi; Naofumi Homma; Shivam Bhasin; Jean-Luc Danger (HOST, 2014)

12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. - Noriyuki Miura; Shiro Dosho; Satoshi Takaya; Daisuke Fujimoto; Takuya Kiriyama; Hiroyuki Tezuka; Takuji Miki; Hiroto Yanagawa; Makoto Nagata (ISSCC, 2014)

A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils. - Taisuke Hayashi; Noriyuki Miura; Kumpei Yoshikawa; Makoto Nagata (VLSI-DAT, 2014)

A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. - Noriyuki Miura; Daisuke Fujimoto; Daichi Tanaka; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Makoto Nagata (VLSIC, 2014)

EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. - Naofumi Homma; Yu-ichi Hayashi; Noriyuki Miura; Daisuke Fujimoto; Daichi Tanaka; Makoto Nagata; Takafumi Aoki (IACR Cryptol. ePrint Arch., 2014)

Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. - Naoya Azuma; Shunsuke Shimazaki; Noriyuki Miura; Makoto Nagata; Tomomitsu Kitamura; Satoru Takahashi; Motoki Murakami; Kazuaki Hori; Atsushi Nakamura; Kenta Tsukamoto; Mizuki Iwanami; Eiji Hankui; et al. (IEICE Trans. Electron., 2014)

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. - Daisuke Fujimoto; Noriyuki Miura; Makoto Nagata; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Yohei Hori; Toshihiro Katashita; Kazuo Sakiyama; Thanh-Ha Le; Julien Bringer; Pirouz Bazargan-Sabet; et al. (IEICE Trans. Electron., 2014)

A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. - Atsutake Kosuge; Wataru Mizuhara; Tsunaaki Shidei; Tsutomu Takeya; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2014)

A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. - Daisuke Fujimoto; Noriyuki Miura; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Makoto Nagata (ASP-DAC, 2015)

EM attack sensor: concept, circuit, and design-automation methodology. - Noriyuki Miura; Daisuke Fujimoto; Makoto Nagata; Naofumi Homma; Yu-ichi Hayashi; Takafumi Aoki (DAC, 2015)

At-Product-Test Dedicated Adaptive supply-resonance suppression. - Kohki Taniguchi; Noriyuki Miura; Taisuke Hayashi; Makoto Nagata (VTS, 2015)

A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. - Noriyuki Miura; Shiro Dosho; Hiroyuki Tezuka; Takuji Miki; Daisuke Fujimoto; Takuya Kiriyama; Makoto Nagata (IEEE J. Solid State Circuits, 2015)

PLL to the rescue: a novel EM fault countermeasure. - Noriyuki Miura; Zakaria Najm; Wei He 015; Shivam Bhasin; Xuan Thuy Ngo; Makoto Nagata; Jean-Luc Danger (DAC, 2016)

A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. - Takuji Miki; Noriyuki Miura; Kento Mizuta; Shiro Dosho; Makoto Nagata (ESSCIRC, 2016)

Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection. - Wei He 015; Jakub Breier; Shivam Bhasin; Noriyuki Miura; Makoto Nagata (FDTC, 2016)

On-chip substrate-bounce monitoring for laser-fault countermeasure. - Kohei Matsuda; Noriyuki Miura; Makoto Nagata; Yu-ichi Hayashi; Tatsuya Fujii; Kazuo Sakiyama (AsianHOST, 2016)

Attack sensing against EM leakage and injection. - Noriyuki Miura; Shivam Bhasin (ISOCC, 2016)

Introduction to the Special Section on the 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC). - Makoto Ikeda; Noriyuki Miura (IEEE J. Solid State Circuits, 2016)

An FPGA-compatible PLL-based sensor against fault injection attack. - Wei He 015; Jakub Breier; Shivam Bhasin; Noriyuki Miura; Makoto Nagata (ASP-DAC, 2017)

Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF. - Noriyuki Miura; Masanori Takahashi; Kazuki Nagatomo; Makoto Nagata (A-SSCC, 2017)

Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis. - Takeshi Sugawara 001; Natsu Shoji; Kazuo Sakiyama; Kohei Matsuda; Noriyuki Miura; Makoto Nagata (FDTC, 2017)

15.8 A permanent digital archive system based on 4F2 x-point multi-layer metal nano-dot structure. - Noriyuki Miura; Shijia Liu; Tsuyoshi Watanabe; Shigeki Imai; Makoto Nagata (ISSCC, 2017)

Protecting cryptographic integrated circuits with side-channel information. - Makoto Nagata; Daisuke Fujimoto; Noriyuki Miura; Naofumi Homma; Yu-ichi Hayashi; Kazuo Sakiyama (IEICE Electron. Express, 2017)

A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. - Takuji Miki; Noriyuki Miura; Kento Mizuta; Shiro Dosho; Makoto Nagata (IEICE Trans. Electron., 2017)

Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. - Naofumi Homma; Yu-ichi Hayashi; Noriyuki Miura; Daisuke Fujimoto; Makoto Nagata; Takafumi Aoki (J. Cryptol., 2017)

Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. - Jean-Luc Danger; Risa Yashiro; Tarik Graba; Yves Mathieu; Abdelmalek Si-Merabet; Kazuo Sakiyama; Noriyuki Miura; Makoto Nagata (DSD, 2018)

A 286F2/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack. - Kohei Matsuda; Tatsuya Fujii; Natsu Shoji; Takeshi Sugawara 001; Kazuo Sakiyama; Yu-ichi Hayashi; Makoto Nagata; Noriyuki Miura (ISSCC, 2018)

A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor. - Kohei Matsuda; Tatsuya Fujii; Natsu Shoji; Takeshi Sugawara 001; Kazuo Sakiyama; Yu-ichi Hayashi; Makoto Nagata; Noriyuki Miura (IEEE J. Solid State Circuits, 2018)

Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor. - Noriyuki Miura; Masanori Takahashi; Kazuki Nagatomo; Makoto Nagata (IEEE J. Solid State Circuits, 2018)

A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. - Daisuke Fujimoto; Shota Nin; Yu-ichi Hayashi; Noriyuki Miura; Makoto Nagata; Tsutomu Matsumoto (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. - Takuji Miki; Makoto Nagata; Akihiro Tsukioka; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (3DIC, 2019)

A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar. - Noriyuki Miura; Tatsuya Machida; Kohei Matsuda; Makoto Nagata; Shoei Nashimoto; Daisuke Suzuki (ASHES@CCS, 2019)

On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. - Makoto Nagata; Takuji Miki; Noriyuki Miura (CICC, 2019)

Side-Channel Leakage of Alarm Signal for a Bulk-Current-Based Laser Sensor. - Yang Li 001; Ryota Hatano; Sho Tada; Kohei Matsuda; Noriyuki Miura; Takeshi Sugawara 001; Kazuo Sakiyama (Inscrypt, 2019)

A 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes. - Takuji Miki; Noriyuki Miura; Makoto Nagata (IEICE Trans. Electron., 2019)

Side-channel leakage from sensor-based countermeasures against fault injection attack. - Takeshi Sugawara 001; Natsu Shoji; Kazuo Sakiyama; Kohei Matsuda; Noriyuki Miura; Makoto Nagata (Microelectron. J., 2019)

A Key Recovery Algorithm Using Random Key Leakage from AES Key Schedule. - Tomoki Uemura; Yohei Watanabe 001; Yang Li 001; Noriyuki Miura; Mitsugu Iwamoto; Kazuo Sakiyama; Kazuo Ohta (ISITA, 2020)

Flush Code Eraser: Fast Attack Response Invalidating Cryptographic Sensitive Data. - Kazuo Sakiyama; Tatsuya Fujii; Kohei Matsuda; Noriyuki Miura (IEEE Embed. Syst. Lett., 2020)

A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation. - Yoshihide Komatsu; Akinori Shinmyo; Mayuko Fujita; Tsuyoshi Hiraki; Kouichi Fukuda; Noriyuki Miura; Makoto Nagata (IEICE Trans. Electron., 2020)

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. - Takuji Miki; Makoto Nagata; Hiroki Sonoda; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEEE J. Solid State Circuits, 2020)

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. - Rei Ueno; Naofumi Homma; Sumio Morioka; Noriyuki Miura; Kohei Matsuda; Makoto Nagata; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean-Luc Danger (IEEE Trans. Computers, 2020)

A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. - Takuji Miki; Noriyuki Miura; Hiroki Sonoda; Kento Mizuta; Makoto Nagata (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

More Accurate and Robust PRNU-Based Source Camera Identification with 3-Step 3-Class Approach. - Annjhih Hsiao; Takao Takenouchi; Hiroaki Kikuchi; Kazuo Sakiyama; Noriyuki Miura (IWDW, 2021)

Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure. - Shoei Nashimoto; Daisuke Suzuki; Noriyuki Miura; Tatsuya Machida; Kohei Matsuda; Makoto Nagata (J. Cryptogr. Eng., 2021)

Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. - Ville Yli-Mäyry; Rei Ueno; Noriyuki Miura; Makoto Nagata; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean-Luc Danger; Naofumi Homma (IEEE Trans. Inf. Forensics Secur., 2021)

DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification. - Dehua Liang; Jun Shiomi; Noriyuki Miura; Hiromitsu Awano (ASP-DAC, 2022)

Accurate measurement of charge density in nanoscale particles using an aperture optimization of Fourier based phase reconstruction. - Takuma Okada; Yoshihiro Midoh; Koji Nakamae; Noriyuki Miura (Computational Imaging, 2022)

A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. - Dehua Liang; Jun Shiomi; Noriyuki Miura; Masanori Hashimoto; Hiromitsu Awano (IEICE Trans. Inf. Syst., 2022)

Physical Attack Protection Techniques for IC Chip Level Hardware Security. - Makoto Nagata; Takuji Miki; Noriyuki Miura (IEEE Trans. Very Large Scale Integr. Syst., 2022)

DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits. - Dehua Liang; Hiromitsu Awano; Noriyuki Miura; Jun Shiomi (ASP-DAC, 2023)

A Triturated Sensing System. - Noriyuki Miura; Kotaro Naruse; Jun Shiomi; Yoshihiro Midoh; Tetsuya Hirose; Takaaki Okidono; Takuji Miki; Makoto Nagata (ISSCC, 2023)

A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication. - Kotaro Naruse; Takayuki Ueda; Jun Shiomi; Yoshihiro Midoh; Noriyuki Miura (ISSCC, 2023)

Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits. - Kazuki Minamiguchi; Yoshihiro Midoh; Noriyuki Miura; Jun Shiomi (ASPDAC, 2024)

Edge-Oriented Point Cloud Compression by Moving Object Detection for Realtime Smart Monitoring. - Itsuki Takada; Daiki Nitto; Yoshihiro Midoh; Noriyuki Miura; Jun Shiomi; Ryoichi Shinkuma (CCNC, 2024)

SecONN: An Optical Neural Network Framework with Concurrent Detection of Thermal Fault Injection Attacks. - Kota Nishida; Yoshihiro Midoh; Noriyuki Miura; Satoshi Kawakami; Jun Shiomi (CoRR, 2024)

StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification. - Dehua Liang; Jun Shiomi; Noriyuki Miura; Hiromitsu Awano (IEEE Open J. Circuits Syst., 2024)

All You Need Is Fault: Zero-Value Attacks on AES and a New λ-Detection M&M. - Haruka Hirata; Daiki Miyahara; Victor Arribas; Yang Li 001; Noriyuki Miura; Svetla Nikova; Kazuo Sakiyama (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits. - Dehua Liang; Hiromitsu Awano; Noriyuki Miura; Jun Shiomi (ACM Trans. Embed. Comput. Syst., 2024)

Hardware Trojan Detection by Fine-grained Power Domain Partitioning. - Takahiro Ishikawa; Kose Yokooji; Yoshihiro Midoh; Noriyuki Miura; Michihiro Shintani; Jun Shiomi (ASP-DAC, 2025)

20.1 A 3.5×3.5mm2 1.47mW/ch 16-Channel MSS-CMOS Heterogeneous Multi-Modal-Gas-Sensor Chip Stack. - Kotaro Naruse; Naru Kato; Takuma Matsumori; Jun Shiomi; Yoshihiro Midoh; Tetsuya Hirose; Gaku Imamura; Genki Yoshikawa; Constantine Sideris; Noriyuki Miura (ISSCC, 2025)