A multiprocessor architecture for multiple path stack sequential decoders. - Normand Bélanger; David Haccoun; Yvon Savaria (IEEE Trans. Commun., 1994)

Application specific instruction-set processor generation for video processing based on loop optimization. - Maria Mbaye; Normand Bélanger; Yvon Savaria; Samuel Pierre (ISCAS (4), 2005)

Design exploration with an application-specific instruction-set processor for ELA deinterlacing. - Maria Mbaye; D. Lebel; Normand Bélanger; Yvon Savaria; Samuel Pierre (ISCAS, 2006)

Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. - Nicolas Beucher; Normand Bélanger; Yvon Savaria; Guy Bois (SiPS, 2006)

A Methodology to Evaluate the Energy Efficiency of Application Specific Processors. - Nicolas Beucher; Normand Bélanger; Yvon Savaria; Guy Bois (ICECS, 2007)

A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration. - Mame Maria Mbaye; Normand Bélanger; Yvon Savaria; Samuel Pierre (J. VLSI Signal Process., 2007)

Loop-oriented metrics for exploring an application-specific architecture design-space. - Maria Mbaye; Normand Bélanger; Yvon Savaria; Samuel Pierre (ASAP, 2008)

High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. - Nicolas Beucher; Normand Bélanger; Yvon Savaria; Guy Bois (J. Signal Process. Syst., 2009)

Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. - Syed Rafay Hasan; Normand Bélanger; Yvon Savaria; M. Omair Ahmad (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. - Syed Rafay Hasan; Normand Bélanger; Yvon Savaria; M. Omair Ahmad (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A GPGPU-based software implementation of the PBDI deinterlacing algorithm. - Gilbert Kowarzyk; Normand Bélanger; Yvon Savaria (ICECS, 2011)

All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. - Syed Rafay Hasan; Normand Bélanger; Yvon Savaria; M. Omair Ahmad (Integr., 2011)

Loop Acceleration Exploration for ASIP Architecture. - Mame Maria Mbaye; Normand Bélanger; Yvon Savaria; Samuel Pierre (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Optimal packet classification applicable tothe OpenFlow context. - Thibaut Stimpfling; Yvon Savaria; André Béliveau; Normand Bélanger; Omar Cherkaoui (HPPN@HPDC, 2013)

Efficient Parallel Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. - Gilbert Kowarzyk; Normand Bélanger; David Haccoun; Yvon Savaria (IEEE Trans. Commun., 2013)

Optimizing the Parallel Tree-Search for Finding Shortest-Span Error-Correcting CDO Codes. - Gilbert Kowarzyk; Normand Bélanger; David Haccoun; Yvon Savaria (IEEE Trans. Parallel Distributed Syst., 2014)

Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum. - Hanieh Abdollahifakhr; Normand Bélanger; Yvon Savaria; François Gagnon (NEWCAS, 2015)

DPDK and MKL; Enabling technologies for near deterministic cloud-based signal processing. - Roya Alizadeh; Normand Bélanger; Yvon Savaria; Jean-François Frigon (NEWCAS, 2015)

Performance characterization of an SCMA decoder. - Roya Alizadeh; Normand Bélanger; Yvon Savaria; François R. Boyer (NEWCAS, 2016)

A fast systolic priority queue architecture for a flow-based Traffic Manager. - Imad Benacer; François-Raymond Boyer; Normand Bélanger; Yvon Savaria (NEWCAS, 2016)

Extensions to decision-tree based packet classification algorithms to address new classification paradigms. - Thibaut Stimpfling; Normand Bélanger; Omar Cherkaoui; André Béliveau; Ludovic Béliveau; Yvon Savaria (Comput. Networks, 2017)

A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis. - Thibaut Stimpfling; J. M. Pierre Langlois; Normand Bélanger; Yvon Savaria (CCGrid, 2018)

Implementation of a Cache-Based IPv6 Lookup System with Hashing. - Bachir Fradj; Benjamin Wolff; Normand Bélanger; Yvon Savaria (ISCAS, 2018)

Extending a CPU Cache for Efficient IPv6 Lookup. - Benjamin Wolff; Bachir Fradj; Normand Bélanger; Yvon Savaria (MWSCAS, 2018)

SHIP: A Scalable High-Performance IPv6 Lookup Algorithm That Exploits Prefix Characteristics. - Thibaut Stimpfling; Normand Bélanger; J. M. Pierre Langlois; Yvon Savaria (IEEE/ACM Trans. Netw., 2019)