Programmable impulse neural circuits. - Jack L. Meador; Angus Wu; Clint S. Cole; Novat Nintunze; Pichet Chintrakulchai (IEEE Trans. Neural Networks, 1991)

An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin. - Cangsang Zhao; Uddalak Bhattacharya; Martin Denham; Jim Kolousek; Yi Lu; Yong-Gee Ng; Novat Nintunze; Kamal Sarkez; Hemmige D. Varadarajan (IEEE J. Solid State Circuits, 1999)