A 1.5-V full-swing BiCMOS logic circuit. - Mitsuru Hiraki; Kazuo Yano; Masataka Minami; Kazushige Sato; Nozomu Matsuzaki; Atsuo Watanabe; Takashi Nishida; Katsuro Sasaki; Koichi Seki (IEEE J. Solid State Circuits, 1992)

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. - Hiroyuki Mizuno; Nozomu Matsuzaki; Kenichi Osada; Toshinobu Shinbo; Nagatoshi Ohki; Hiroshi Ishida; Koichiro Ishibashi; Tokuo Kure (IEEE J. Solid State Circuits, 1996)

Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. - Kenichi Osada; Takayuki Kawahara; Riichiro Takemura; Naoki Kitai; Norikatsu Takaura; Nozomu Matsuzaki; Kenzo Kurotsuchi; Hiroshi Moriya; Masahiro Moniwa (CICC, 2005)

A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. - Satoru Hanzawa; Naoki Kitai; Kenichi Osada; Akira Kotabe; Yuichi Matsui; Nozomu Matsuzaki; Norikatsu Takaura; Masahiro Moniwa; Takayuki Kawahara (ISSCC, 2007)

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. - Riichiro Takemura; Takayuki Kawahara; Katsuya Miura; Hiroyuki Yamamoto; Jun Hayakawa; Nozomu Matsuzaki; Kazuo Ono; Michihiko Yamanouchi; Kenchi Ito; Hiromasa Takahashi; Shoji Ikeda; Haruhiro Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)