A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. - Nozomu Togawa; Masao Sato; Tatsuo Ohtsuki (ICCAD, 1994)

A Simultaneous Placement and Global Routing Algorithm for FPGAs. - Nozomu Togawa; Masao Sato; Tatsuo Ohtsuki (ISCAS, 1994)

Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. - Nozomu Togawa; Masao Sato; Tatsuo Ohtsuki (ASP-DAC, 1995)

A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. - Nozomu Togawa; Masao Sato; Tatsuo Ohtsuki (ASP-DAC, 1997)

A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems. - Nozomu Togawa; Masao Sato; Tatsuo Ohtsuki (J. Circuits Syst. Comput., 1997)

A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. - Nozomu Togawa; Takafumi Hisaki; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 1998)

An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. - Nozomu Togawa; Kayoko Hagi; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 1998)

Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. - Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. - Nozomu Togawa; Takashi Sakurai; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 1999)

A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. - Nozomu Togawa; Kaoru Ukai; Masao Yanagisawa; Tatsuo Ohtsuki (J. Circuits Syst. Comput., 1999)

An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). - Nozomu Togawa; Masayuki Ienaga; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2000)

Area/delay estimation for digital signal processor cores. - Yuichiro Miyaoka; Yoshiharu Kataoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2001)

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. - Yuichiro Miyaoka; Jinku Choi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (APCCAS (1), 2002)

VLSI Architecture for a Flexible Motion Estimation with Parameters. - Jinku Choi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC/VLSI Design, 2002)

An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation. - Jinku Choi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks. - Shinichi Noda; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation. - Shinichi Noda; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A hardware/software partitioning algorithm for SIMD processor cores. - Koichi Tachikake; Nozomu Togawa; Yuichiro Miyaoka; Jinku Choi; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2003)

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. - Nozomu Togawa; Kyosuke Kasahara; Yuichiro Miyaoka; Jinku Choi; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories. - Nozomu Togawa; Takao Totsuka; Tatsuhiko Wakui; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A cosynthesis algorithm for application specific processors with heterogeneous datapaths. - Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2004)

Instruction set and functional unit synthesis for SIMD processor cores. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2004)

A thread partitioning algorithm in low power high-level synthesis. - Jumpei Uchida; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2004)

Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. - Youhua Shi; Shinji Kimura; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (Asian Test Symposium, 2004)

Reconfigurable adaptive FEC system with interleaving. - Kazunori Shimizu; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (ASP-DAC, 2005)

A processor core synthesis system in IP-based SoC design. - Naoki Tomono; Shunitsu Kohara; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2005)

Low Power Test Compression Technique for Designs with Multiple Scan Chain. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki; Shinji Kimura (Asian Test Symposium, 2005)

Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. - Kazunori Shimizu; Tatsuyuki Ishikawa; Takeshi Ikenaga; Satoshi Goto; Nozomu Togawa (ICCD, 2005)

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. - Nozomu Togawa; Hideki Kawazu; Jumpei Uchida; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (ISCAS (4), 2005)

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. - Hideki Kawazu; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving. - Kazunori Shimizu; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Inf. Syst., 2005)

A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. - Nozomu Togawa; Koichi Tachikake; Yuichiro Miyaoka; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Inf. Syst., 2005)

Memory-Efficient Accelerating Schedule for LDPC Decoder. - Kazunori Shimizu; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (APCCAS, 2006)

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. - Shunitsu Kohara; Naoki Tomono; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2006)

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. - Youhua Shi; Nozomu Togawa; Shinji Kimura; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2006)

A parallel LSI architecture for LDPC decoder improving message-passing schedule. - Kazunori Shimizu; Tatsuyuki Ishikawa; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (ISCAS, 2006)

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. - Youhua Shi; Nozomu Togawa; Shinji Kimura; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule. - Kazunori Shimizu; Tatsuyuki Ishikawa; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. - Kazunori Shimizu; Tatsuyuki Ishikawa; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. - Jumpei Uchida; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Electron., 2006)

Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ISCAS, 2007)

Power-efficient LDPC code decoder architecture. - Kazunori Shimizu; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (ISLPED, 2007)

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. - Akiyuki Nagashima; Yuta Imai; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (APCCAS, 2008)

Unknown response masking with minimized observable response loss and mask data. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (APCCAS, 2008)

FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm. - Ryo Tamura; Masayuki Honma; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki; Makoto Satoh (APCCAS, 2008)

GECOM: Test data compression combined with all unknown response masking. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2008)

Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). - Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Kazunori Shimizu; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2008)

A Secure Test Technique for Pipelined Advanced Encryption Standard. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Inf. Syst., 2008)

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique. - Kazunori Shimizu; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. - Akira Ohchi; Shunitsu Kohara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Exact and fast L1 cache simulation for embedded systems. - Nobuaki Tojo; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2009)

Design-for-secure-test for crypto cores. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ITC, 2009)

A Scan-Based Attack Based on Discriminators for AES Cryptosystems. - Ryuta Nara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. - Akira Ohchi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). - Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An L1 Cache Design Space Exploration System for Embedded Applications. - Nobuaki Tojo; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A Two-Level Cache Design Space Exploration System for Embedded Applications. - Nobuaki Tojo; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers. - Seungju Lee; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (APCCAS, 2010)

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. - Youhua Shi; Kenta Tokumitsu; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (APCCAS, 2010)

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. - Youhei Tsukamoto; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (APCCAS, 2010)

Scan-based attack against elliptic curve cryptosystems. - Ryuta Nara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2010)

State-dependent changeable scan architecture against scan-based side channel attacks. - Ryuta Nara; Hiroshi Atobe; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ISCAS, 2010)

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. - Akira Ohchi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ISCAS, 2010)

Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures. - Ryuta Nara; Kei Satoh; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Improved Launch for Higher TDF Coverage With Fewer Test Patterns. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Speeding-up exact and fast FIFO-based cache configuration simulation. - Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Electron. Express, 2011)

Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint. - Mikiko Sode Tanaka; Nozomu Togawa; Masao Yanagisawa; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint. - Mikiko Sode Tanaka; Nozomu Togawa; Masao Yanagisawa; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Scan Vulnerability in Elliptic Curve Cryptosystems. - Ryuta Nara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures. - Sho Tanaka; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. - Masashi Tawada; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. - Youhei Tsukamoto; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. - Yuta Atobe; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2012)

Scan-based attack against DES cryptosystems using scan signatures. - Hirokazu Kodera; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2012)

A hybrid NoC architecture utilizing packet transmission priority control method. - Seungju Lee; Nozomu Togawa; Yusuke Sekihara; Takashi Aoki; Akira Onozawa (APCCAS, 2012)

Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. - Hiromine Yoshihara; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2012)

An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. - Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2012)

A novel BMNoC configuration algorithm utilizing communication volume and locality among cores. - Seungju Lee; Nozomu Togawa; Takashi Aoki; Akira Onozawa (ISCAS, 2012)

Energy-efficient high-level synthesis for HDR architectures with clock gating. - Hiroyuki Akasaka; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2012)

Dynamically changeable secure scan architecture against scan-based side channel attack. - Yuta Atobe; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2012)

MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures. - Shin-ya Abe; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (IEICE Electron. Express, 2012)

A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores. - Seungju Lee; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Scan-Based Attack on AES through Round Registers and Its Countermeasure. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Energy-efficient High-level Synthesis for HDR Architectures. - Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution. - Hiromine Yoshihara; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. - Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Scan-based attack against Trivium stream cipher independent of scan structure. - Mika Fujishiro; Masao Yanagisawa; Nozomu Togawa (ASICON, 2013)

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. - Shota Matsuno; Masashi Tawada; Masao Yanagisawa; Shinji Kimura; Nozomu Togawa; Tadahiko Sugibayashi (ASICON, 2013)

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. - Hiroaki Igarashi; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2013)

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. - Kazushi Kawamura; Sho Tanaka; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2013)

Suspicious timing error prediction with in-cycle clock gating. - Youhua Shi; Hiroaki Igarashi; Nozomu Togawa; Masao Yanagisawa (ISQED, 2013)

Secure Scan Design with Dynamically Configurable Connection. - Yuta Atobe; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (PRDC, 2013)

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. - Shin-ya Abe; Youhua Shi; Kimiyoshi Usami; Masao Yanagisawa; Nozomu Togawa (VLSI-DAT, 2013)

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. - Shin-ya Abe; Youhua Shi; Kimiyoshi Usami; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation. - Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. - Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. - Hiroyuki Akasaka; Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures. - Hirokazu Kodera; Masao Yanagisawa; Nozomu Togawa (J. Inf. Process., 2013)

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. - Koichi Fujiwara; Shin-ya Abe; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

Scan-based side-channel attack on Camellia cipher using scan signatures. - Huiqian Hang; Mika Fujishiro; Hirokazu Kodera; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

A write-reducing and error-correcting code generation method for non-volatile memories. - Tatsuro Kojo; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

Secure scan design using improved random order and its evaluations. - Masaru Oya; Yuta Atobe; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

In-situ timing monitoring methods for variation-resilient designs. - Youhua Shi; Nozomu Togawa (APCCAS, 2014)

A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. - Kotaro Terada; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. - Shinnosuke Yoshida; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

Scan-based attack on the LED block cipher using scan signatures. - Mika Fujishiro; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2014)

Linear and bi-linear interpolation circuits using selector logics and their evaluations. - Masashi Shio; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2014)

Throughput driven check point selection in suspicious timing error prediction based designs. - Hiroaki Igarashi; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (LASCAS, 2014)

Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures. - Mika Fujishiro; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Scan-Based Side-Channel Attack on the LED Block Cipher Using Scan Signatures. - Mika Fujishiro; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. - Hiroyuki Akasaka; Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. - Yuta Hagio; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

Clock skew estimate modeling for FPGA high-level synthesis and its application. - Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ASICON, 2015)

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. - Keita Igarashi; Masao Yanagisawa; Nozomu Togawa (ASICON, 2015)

Small-sized and noise-reducing power analyzer design for low-power IoT devices. - Ryosuke Kitayama; Takashi Takenaka; Masao Yanagisawa; Nozomu Togawa (ASICON, 2015)

A low-power soft error tolerant latch scheme. - Saki Tajima; Youhua Shi; Nozomu Togawa; Masao Yanagisawa (ASICON, 2015)

Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. - Shinnosuke Yoshida; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ASICON, 2015)

A bit-write reduction method based on error-correcting codes for non-volatile memories. - Masashi Tawada; Shinji Kimura; Masao Yanagisawa; Nozomu Togawa (ASP-DAC, 2015)

A score-based classification method for identifying hardware-trojans at gate-level netlists. - Masaru Oya; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (DATE, 2015)

A landmark-based route recommendation method for pedestrian walking strategies. - Siya Bao; Tomoyuki Nitta; Daisuke Shindou; Masao Yanagisawa; Nozomu Togawa (GCCE, 2015)

A visible corner-landmark based route finding algorithm for pedestrian navigation. - Kengo Takeda; Tomoyuki Nitta; Daisuke Shindou; Masao Yanagisawa; Nozomu Togawa (GCCE, 2015)

Effective Parallel Algorithm for GPGPU-Accelerated Explicit Routing Optimization. - Kou Kikuta; Eiji Oki; Naoaki Yamanaka; Nozomu Togawa; Hidenori Nakazato (GLOBECOM, 2015)

Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. - Tatsuro Kojo; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (ICCAD, 2015)

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. - Kotaro Terada; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2015)

A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. - Koki Igawa; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (SoCC, 2015)

Partitioning-based multiplexer network synthesis for field-data extractors. - Koki Ito; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (SoCC, 2015)

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. - Shin-ya Abe; Youhua Shi; Kimiyoshi Usami; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. - Koichi Fujiwara; Kazushi Kawamura; Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures. - Huiqian Jiang; Mika Fujishiro; Hirokazu Kodera; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. - Tatsuro Kojo; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. - Masaru Oya; Youhua Shi; Noritaka Yamashita; Toshihiko Okamura; Yukiyasu Tsunoo; Satoshi Goto; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. - Masashi Tawada; Shinji Kimura; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures. - Kotaro Terada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead. - Shinnosuke Yoshida; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Implementation evaluation of scan-based attack against a Trivium cipher circuit. - Daisuke Oku; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2016)

A safe and comprehensive route finding method for pedestrian based on lighting and landmark. - Siya Bao; Tomoyuki Nitta; Kazuaki Ishikawa; Masao Yanagisawa; Nozomu Togawa (GCCE, 2016)

Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning. - Keisuke Kono; Tomoyuki Nitta; Kazuaki Ishikawa; Masao Yanagisawa; Nozomu Togawa (GCCE, 2016)

Pedestrian navigation based on landmark recognition using glass-type wearable devices. - Ryoya Yano; Tomoyuki Nitta; Kazuaki Ishikawa; Masao Yanagisawa; Nozomu Togawa (GCCE, 2016)

Hardware Trojans classification for gate-level netlists based on machine learning. - Kento Hasegawa; Masaru Oya; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2016)

Redesign for untrusted gate-level netlists. - Masaru Oya; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2016)

Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices. - Ryosuke Kitayama; Takashi Takenaka; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2016)

A high-performance circuit design algorithm using data dependent approximation. - Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2016)

Hash-table and balanced-tree based FIB architecture for CCN routers. - Kenta Shimazaki; Takashi Aoki; Takahiro Hatano; Takuya Otsuka; Akihiko Miyazaki; Toshitaka Tsuda; Nozomu Togawa (ISOCC, 2016)

A delay variation and floorplan aware high-level synthesis algorithm with body biasing. - Koki Igawa; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ISQED, 2016)

In-situ Trojan authentication for invalidating hardware-Trojan functions. - Masaru Oya; Youhua Shi; Masao Yanagisawa; Nozomu Togawa (ISQED, 2016)

Rotator-based multiplexer network synthesis for field-data extractors. - Koki Ito; Kazushi Kawamura; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (SoCC, 2016)

Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms. - Koki Igawa; Masao Yanagisawa; Nozomu Togawa (IEICE Electron. Express, 2016)

Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. - Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design. - Koki Igawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Bi-Partitioning Based Multiplexer Network for Field-Data Extractors. - Koki Ito; Kazushi Kawamura; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices. - Ryosuke Kitayama; Takashi Takenaka; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories. - Tatsuro Kojo; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching. - Masaru Oya; Noritaka Yamashita; Toshihiko Okamura; Yukiyasu Tsunoo; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Message from the Editor-in-Chief. - Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2016)

Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. - Daiki Asai; Masao Yanagisawa; Nozomu Togawa (ASICON, 2017)

Designing hardware trojans and their detection based on a SVM-based approach. - Tomotaka Inoue; Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (ASICON, 2017)

Soft error tolerant latch designs with low power consumption (invited paper). - Saki Tajima; Nozomu Togawa; Masao Yanagisawa; Youhua Shi (ASICON, 2017)

A low cost and high speed CSD-based symmetric transpose block FIR implementation. - Jinghao Ye; Youhua Shi; Nozomu Togawa; Masao Yanagisawa (ASICON, 2017)

A stayed location estimation method for sparse GPS positioning information. - Sae Iwata; Tomoyuki Nitta; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (GCCE, 2017)

An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons. - Ryoya Momose; Tomoyuki Nitta; Masao Yanagisawa; Nozomu Togawa (GCCE, 2017)

Personalized one-day travel with multi-nearby-landmark recommendation. - Siya Bao; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2017)

A robust scan-based side-channel attack method against HMAC-SHA-256 circuits. - Daisuke Oku; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2017)

Hardware Trojans classification for gate-level netlists using multi-layer neural networks. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2017)

Hardware Trojan detection and classification based on steady state learning. - Masaru Oya; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2017)

Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2017)

Effective write-reduction method for MLC non-volatile memory. - Masashi Tawada; Shinji Kimura; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2017)

A selector-based FFT processor and its FPGA implementation. - Yuya Hirai; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2017)

Robust AES circuit design for delay variation using suspicious timing error prediction. - Yuki Yahagi; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2017)

A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions. - Siya Bao; Tomoyuki Nitta; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation. - Koki Igawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations. - Koki Ito; Kazushi Kawamura; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures. - Kotaro Terada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Capacitance Measurement of Running Hardware Devices and its Application to Malicious Modification Detection. - Makoto Nishizawa; Kento Hasegawa; Nozomu Togawa (APCCAS, 2018)

Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis. - Siya Bao; Masao Yanagisawa; Nozomu Togawa (IEEE BigData, 2018)

Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach. - Tomotaka Inoue; Kento Hasegawa; Yuki Kobayashi; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2018)

Robust Indoor/Outdoor Detection Method based on Sparse GPS Positioning Information. - Sae Iwata; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2018)

A Multiple Cyclic-Route Generation Method for Strolling Based on Point-of-Interests. - Tensei Nishimura; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2018)

Bicycle Behavior Recognition using Sensors Equipped with Smartphone. - Yuri Usami; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (ICCE-Berlin, 2018)

Road-illuminance level inference across road networks based on Bayesian analysis. - Siya Bao; Masao Yanagisawa; Nozomu Togawa (ICCE, 2018)

A hardware-Trojan classification method utilizing boundary net structures. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (ICCE, 2018)

Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2018)

An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2018)

A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2018)

A loop structure optimization targeting high-level synthesis of fast number theoretic transform. - Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ISQED, 2018)

2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (NGCAS, 2018)

Hardware Trojan Detection Utilizing Machine Learning Approaches. - Kento Hasegawa; Youhua Shi; Nozomu Togawa (TrustCom/BigDataSE, 2018)

An Ising model mapping to solve rectangle packing problem. - Kotaro Terada; Daisuke Oku; Sho Kanamaru; Shu Tanaka; Masato Hayashi; Masanao Yamaoka; Masao Yanagisawa; Nozomu Togawa (VLSI-DAT, 2018)

Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs. - Ken Hayamizu; Nozomu Togawa; Masao Yanagisawa; Youhua Shi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal. - Sae Iwata; Tomoyuki Nitta; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories. - Tatsuro Kojo; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning. - Masaru Oya; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. - Saki Tajima; Nozomu Togawa; Masao Yanagisawa; Youhua Shi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures. - Daisuke Oku; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2018)

A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments. - Siya Bao; Masao Yanagisawa; Nozomu Togawa (ICIS (best papers), 2019)

Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists. - Kohei Nozawa; Kento Hasegawa; Seira Hidano; Shinsaku Kiyomoto; Kazuo Hashimoto; Nozomu Togawa (CyberICPS/SECPRE/SPOSE/ADIoT@ESORICS, 2019)

A Route Recommendation Method Based on Personal Preferences by Monte-Carlo Tree Search. - Yuta Ishizaki; Toshinori Takayama; Nozomu Togawa (ICCE-Berlin, 2019)

Mapping Constrained Slot-Placement Problems to Ising Models and its Evaluations by an Ising Machine. - Sho Kanamaru; Kazushi Kawamura; Shu Tanaka; Yoshinori Tomita; Hidetoshi Matsuoka; Kaoru Kawamura; Nozomu Togawa (ICCE-Berlin, 2019)

A Multiple Coefficients Trial Method to Solve Combinatorial Optimization Problems for Simulated-annealing-based Ising Machines. - Kota Takehara; Daisuke Oku; Yoshiki Matsuda; Shu Tanaka; Nozomu Togawa (ICCE-Berlin, 2019)

Efficient Ising Model Mapping for Induced Subgraph Isomorphism Problems Using Ising Machines. - Natsuhito Yoshimura; Masashi Tawada; Shu Tanaka; Junya Arai; Satoshi Yagi; Hiroyuki Uchiyama; Nozomu Togawa (ICCE-Berlin, 2019)

Efficient Ising Model Mapping to Solving Slot Placement Problem. - Sho Kanamaru; Daisuke Oku; Masashi Tawada; Shu Tanaka; Masato Hayashi; Masanao Yamaoka; Masao Yanagisawa; Nozomu Togawa (ICCE, 2019)

Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (ICECS, 2019)

Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board. - Kento Hasegawa; Kazunari Takasaki; Makoto Nishizawa; Ryota Ishikawa; Kazushi Kawamura; Nozomu Togawa (FPT, 2019)

Empirical Evaluation on Anomaly Behavior Detection for Low-Cost Micro-Controllers Utilizing Accurate Power Analysis. - Kento Hasegawa; Kiyoshi Chikamatsu; Nozomu Togawa (IOLTS, 2019)

Error Correction Coding of Stochastic Numbers Using BER Measurement. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IOLTS, 2019)

Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. - Jinghao Ye; Nozomu Togawa; Masao Yanagisawa; Youhua Shi (ISCAS, 2019)

Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder. - Yuta Ideguchi; Norifumi Kamiya; Masashi Tawada; Nozomu Togawa (MWSCAS, 2019)

A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions. - Sae Iwata; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests. - Tensei Nishimura; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines. - Daisuke Oku; Kotaro Terada; Masato Hayashi; Masanao Yamaoka; Shu Tanaka; Nozomu Togawa (IEICE Trans. Inf. Syst., 2019)

Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone. - Yuri Usami; Kazuaki Ishikawa; Toshinori Takayama; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

An FPGA Implementation Method based on Distributed-register Architectures. - Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

FPGA-based Heterogeneous Solver for Three-Dimensional Routing. - Kento Hasegawa; Ryota Ishikawa; Makoto Nishizawa; Kazushi Kawamura; Masashi Tawada; Nozomu Togawa (ASP-DAC, 2020)

Theory of Ising Machines and a Common Software Platform for Ising Machines. - Shu Tanaka; Yoshiki Matsuda; Nozomu Togawa (ASP-DAC, 2020)

A New LDPC Code Decoding Method: Expanding the Scope of Ising Machines. - Masashi Tawada; Shu Tanaka; Nozomu Togawa (ICCE, 2020)

Evaluation on Hardware-Trojan Detection at Gate-Level IP Cores Utilizing Machine Learning Methods. - Tatsuki Kurihara; Kento Hasegawa; Nozomu Togawa (IOLTS, 2020)

An Anomalous Behavior Detection Method for IoT Devices by Extracting Application-Specific Power Behaviors. - Kazunari Takasaki; Kento Hasegawa; Ryoichi Kida; Nozomu Togawa (IOLTS, 2020)

Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (LASCAS, 2020)

Designing Stochastic Number Generators Sharing a Random Number Source based on the Randomization Function. - Masashi Tawada; Nozomu Togawa (NEWCAS, 2020)

Document-Level Sentiment Classification in Japanese by Stem-Based Segmentation with Category and Data-Source Information. - Siya Bao; Nozomu Togawa (ICSC, 2020)

Guiding Principle for Minor-Embedding in Simulated-Annealing-Based Ising Machines. - Tatsuhiko Shirai; Shu Tanaka; Nozomu Togawa (IEEE Access, 2020)

A Capacitance Measurement Device for Running Hardware Devices and Its Evaluations. - Makoto Nishizawa; Kento Hasegawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures. - Kento Hasegawa; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Inf. Syst., 2020)

Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. - Ryota Ishikawa; Masashi Tawada; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

Toward Learning Robust Detectors from Imbalanced Datasets Leveraging Weighted Adversarial Training. - Kento Hasegawa; Seira Hidano; Shinsaku Kiyomoto; Nozomu Togawa (CANS, 2021)

An autonomous driving system utilizing image processing accelerated by FPGA. - Kazunari Takasaki; Kota Hisafuru; Ryotaro Negishi; Kazuki Yamashita; Keisuke Fukada; Tomoya Wakaizumi; Nozomu Togawa (FPT, 2021)

A PDR Method Combining Smartphone and Smartwatch based on Multi-Scenario Map Matching. - Tomoya Wakaizumi; Nozomu Togawa (GCCE, 2021)

Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture. - Shota Matsuno; Masashi Tawada; Nozomu Togawa (ICCE, 2021)

Visiting-Route Recommendation in Amusement Parks and its Evaluations by an Ising Machine. - Yosuke Mukasa; Tomoya Wakaizumi; Shu Tanaka; Nozomu Togawa (ICCE, 2021)

An Indoor Positioning Method using Smartphone and Smartwatch Independent of Carrying Modes. - Tomoya Wakaizumi; Nozomu Togawa (ICCE, 2021)

Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists. - Kento Hasegawa; Seira Hidano; Kohei Nozawa; Shinsaku Kiyomoto; Nozomu Togawa (IOLTS, 2021)

Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random Forests. - Tatsuki Kurihara; Nozomu Togawa (IOLTS, 2021)

An Anomalous Behavior Detection Method Based on Power Analysis Utilizing Steady State Power Waveform Predicted by LSTM. - Kazunari Takasaki; Ryoichi Kida; Nozomu Togawa (IOLTS, 2021)

Multi-day Travel Planning Using Ising Machines for Real-world Applications. - Siya Bao; Masashi Tawada; Shu Tanaka; Nozomu Togawa (ITSC, 2021)

An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines. - Siya Bao; Masashi Tawada; Shu Tanaka; Nozomu Togawa (VLSI-DAT, 2021)

A Three-Stage Annealing Method Solving Slot-Placement Problems Using an Ising Machine. - Keisuke Fukada; Matthieu Parizy; Yoshinori Tomita; Nozomu Togawa (IEEE Access, 2021)

Performance Comparison of Typical Binary-Integer Encodings in an Ising Machine. - Kensuke Tamura; Tatsuhiko Shirai; Hosho Katsura; Shu Tanaka; Nozomu Togawa (IEEE Access, 2021)

A Two-Stage Hardware Trojan Detection Method Considering the Trojan Probability of Neighbor Nets. - Kento Hasegawa; Tomotaka Inoue; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Analysis and Acceleration of the Quadratic Knapsack Problem on an Ising Machine. - Matthieu Parizy; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

An Anomalous Behavior Detection Method Utilizing Extracted Application-Specific Power Behaviors. - Kazunari Takasaki; Ryoichi Kida; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations. - Sho Kanamaru; Kazushi Kawamura; Shu Tanaka; Yoshinori Tomita; Nozomu Togawa (IEICE Trans. Inf. Syst., 2021)

An Ising Machine-Based Solver for Visiting-Route Recommendation Problems in Amusement Parks. - Yosuke Mukasa; Tomoya Wakaizumi; Shu Tanaka; Nozomu Togawa (IEICE Trans. Inf. Syst., 2021)

Mapping Induced Subgraph Isomorphism Problems to Ising Models and Its Evaluations by an Ising Machine. - Natsuhito Yoshimura; Masashi Tawada; Shu Tanaka; Junya Arai; Satoshi Yagi; Hiroyuki Uchiyama; Nozomu Togawa (IEICE Trans. Inf. Syst., 2021)

Experimental Evaluations of Parallel Tempering on an Ising Machine. - Yosuke Mukasa; Shu Tanaka; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2021)

A Route Recommendation Method Considering Individual User's Preferences by Monte-Carlo Tree Search and Its Evaluations. - Yuta Ishizaki; Yurie Koyama; Toshinori Takayama; Nozomu Togawa (J. Inf. Process., 2021)

Generating Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists. - Kohei Nozawa; Kento Hasegawa; Seira Hidano; Shinsaku Kiyomoto; Kazuo Hashimoto; Nozomu Togawa (J. Inf. Process., 2021)

Autonomous driving system with feature extraction using a binarized autoencoder. - Kota Hisafuru; Ryotaro Negishi; Soma Kawakami; Dai Sato; Kazuki Yamashita; Keisuke Fukada; Nozomu Togawa (FPT, 2022)

Hardware-Trojan Detection at Gate-level Netlists using Gradient Boosting Decision Tree Models. - Ryotaro Negishi; Tatsuki Kurihara; Nozomu Togawa (ICCE-Berlin, 2022)

A PDR Method Using Smartglasses Reducing Accumulated Errors by Detecting User's Stop Motions. - Dai Sato; Nozomu Togawa (ICCE, 2022)

Efficient Coefficient Bit-Width Reduction Method for Ising Machines. - Yuta Yachi; Yousuke Mukasa; Masashi Tawada; Nozomu Togawa (ICCE, 2022)

QUBO Matrix Distorting Method for Consumer Applications. - Tomokazu Yoshimura; Tatsuhiko Shirai; Masashi Tawada; Nozomu Togawa (ICCE, 2022)

An Anomalous Behavior Detection Method for IoT Devices Based on Power Waveform Shapes. - Kota Hisafuru; Kazunari Takasaki; Nozomu Togawa (IOLTS, 2022)

Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists. - Kazuki Yamashita; Tomohiro Kato; Kento Hasegawa; Seira Hidano; Kazuhide Fukushima; Nozomu Togawa (IOLTS, 2022)

Cardinality Constrained Portfolio Optimization on an Ising Machine. - Matthieu Parizy; Przemyslaw Sadowski; Nozomu Togawa (SOCC, 2022)

Multi-Objective Trip Planning Based on Ant Colony Optimization Utilizing Trip Records. - Etsushi Saeki; Siya Bao; Toshinori Takayama; Nozomu Togawa (IEEE Access, 2022)

Hardware-Trojan Detection Based on the Structural Features of Trojan Circuits Using Random Forests. - Tatsuki Kurihara; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Carrying-mode Free Indoor Positioning Using Smartphone and Smartwatch and Its Evaluations. - Tomoya Wakaizumi; Nozomu Togawa (J. Inf. Process., 2022)

Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances. - Yuta Atobe; Masashi Tawada; Nozomu Togawa (IEEE Trans. Computers, 2022)

How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins. - Daisuke Oku; Masashi Tawada; Shu Tanaka; Nozomu Togawa (IEEE Trans. Computers, 2022)

A Constrained Graph Coloring Solver Based on Ising Machines. - Soma Kawakami; Yosuke Mukasa; Siya Bao; Dema Ba; Junya Arai; Satoshi Yagi; Junji Teramoto; Nozomu Togawa (ICCE, 2023)

A Quasi-Initial Solution Giving Method for Ising Machines by Controlling External Magnetic Field Coefficients. - Soma Kawakami; Kentaro Ohno; Dema Ba; Satoshi Yagi; Junji Teramoto; Nozomu Togawa (ICCE, 2023)

Fast Hyperparameter Tuning for Ising Machines. - Matthieu Parizy; Norihiro Kakuko; Nozomu Togawa (ICCE, 2023)

Fast and Accurate Smartglass Angles Inference Based on Periodic Behavior in Walking. - Dai Sato; Nozomu Togawa (ICCE, 2023)

Multi-Day Intermodal Travel Planning for Urban Cities Using Ising Machines. - Siya Bao; Nozomu Togawa (ITSC, 2023)

A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output. - Yuta Yachi; Masashi Tawada; Nozomu Togawa (SOCC, 2023)

Membership Inference Attacks against GNN-based Hardware Trojan Detection. - Kento Hasegawa; Kazuki Yamashita; Seira Hidano; Kazuhide Fukushima; Kazuo Hashimoto; Nozomu Togawa (TrustCom, 2023)

Dynamical Process of a Bit-Width Reduced Ising Model With Simulated Annealing. - Shuta Kikuchi; Nozomu Togawa; Shu Tanaka (IEEE Access, 2023)

Trip Planning Based on subQUBO Annealing. - Tatsuya Noguchi; Keisuke Fukada; Siya Bao; Nozomu Togawa (IEEE Access, 2023)

QuDASH: Quantum-Inspired Rate Adaptation Approach for DASH Video Streaming. - Bo Wei 001; Hang Song 001; Makoto Nakamura; Koichi Kimura; Nozomu Togawa; Jiro Katto (IEEE Access, 2023)

Linearization via Ordering Variables in Binary Optimization for Ising Machines. - Kentaro Ohno; Nozomu Togawa (CoRR, 2023)

R-HTDetector: Robust Hardware-Trojan Detection Based on Adversarial Training. - Kento Hasegawa; Seira Hidano; Kohei Nozawa; Shinsaku Kiyomoto; Nozomu Togawa (IEEE Trans. Computers, 2023)

Multi-Spin-Flip Engineering in an Ising Machine. - Tatsuhiko Shirai; Nozomu Togawa (IEEE Trans. Computers, 2023)

An Efficient Combined Bit-Width Reducing Method for Ising Models. - Yuta Yachi; Masashi Tawada; Nozomu Togawa (IEICE Trans. Inf. Syst., 2023)

Spin-Variable Reduction Method for Handling Linear Equality Constraints in Ising Machines. - Tatsuhiko Shirai; Nozomu Togawa (IEEE Trans. Computers, 2023)

Hybrid Iterative Annealing Method Using a Quantum Annealer and a Classical Computer. - Keisuke Fukada; Tatshuhiko Shirai; Nozomu Togawa (ICCE, 2024)

Gen-Power: Anomaly Detection in IoT Devices Utilizing Generated Power Waveforms. - Kota Hisafuru; Nozomu Togawa (ICCE, 2024)

Carrying-Mode-Free Stair Ascent and Descent Estimation using Smartphones. - Dai Kajimoto; Etsushi Saeki; Siya Bao; Nozomu Togawa (ICCE, 2024)

An Interaction Coefficient Control Method for Setting Initial Solutions to Ising Machines. - Soma Kawakami; Kentaro Ohno; Dema Ba; Satoshi Yagi; Junji Teramoto; Nozomu Togawa (ICCE, 2024)

Evaluation of Ensemble Learning Models for Hardware-Trojan Identification at Gate-level Netlists. - Ryotaro Negishi; Nozomu Togawa (ICCE, 2024)

Time-Dependent Multi-Objective Trip Planning by Ant Colony Optimization with Route API. - Etsushi Saeki; Siya Bao; Toshinori Takayama; Nozomu Togawa (ICCE, 2024)

Optimization of Practical Time-Dependent Vehicle Routing Problem by Ising Machines. - Yui Tsuyumine; Kenichi Masuda; Takeshi Hachikawa; Tsuyoshi Haga; Yuta Yachi; Tatsuhiko Shirai; Masashi Tawada; Nozomu Togawa (ICCE, 2024)

Anomalous IoT Behavior Detection by Generated Power Waveforms with Hyper-parameter Tuning. - Ryusei Eda; Kota Hisafuru; Nozomu Togawa (IOLTS, 2024)

Prioritizing Vulnerability Assessment Items Using LLM Based on IoT Device Documentations. - Yuka Ikegami; Ryotaro Negishi; Kento Hasegawa; Seira Hidano; Kazuhide Fukushima; Kazuo Hashimoto; Nozomu Togawa (IOTSMS, 2024)

Initial Seeds Generation Using LLM for IoT Device Fuzzing. - Hibiki Nakanishi; Kota Hisafuru; Kento Hasegawa; Seira Hidano; Kazuhide Fukushima; Kazuo Hashimoto; Nozomu Togawa (IOTSMS, 2024)

A Novel Classical-Ising Hybrid Annealing Method with QUBO Model Cutting. - Yuta Atobe; Masashi Tawada; Nozomu Togawa (MWSCAS, 2024)

Optimization of Base Station Power Supply Selection by Quantum Annealing. - Chihiro Dogo; Kazuhiro Saito; Nozomu Togawa (QCE, 2024)

Large-Sized VQE Performance Profiling in Quantum Chemistry Using a Multi-Node Quantum Simulator. - Keisuke Fukada; Tatsuhiko Shirai; Mikio Morita; Yoshinori Tomita; Koichi Kimura; Nozomu Togawa (QCE, 2024)

Non-zero Coefficients Removing Method to Improve the Ising Machine Solving Performance. - Kinya Iwata; Masashi Tawada; Nozomu Togawa (QCE, 2024)

Multi-Day Intermodal Trip Planning Using subQUBO Annealing with Correction Processing. - Tatsuya Noguchi; Keisuke Fukada; Siya Bao; Nozomu Togawa (QCE, 2024)

Personalized Course Selection Optimization Using an Ising Machine. - Takeru Ota; Keisuke Fukada; Nozomu Togawa (QCE, 2024)

Variable Reduction Method for Quadratic Three-Dimensional Assignment Problem with FMQA. - Sora Tomita; Tatsuhiko Shirai; Nozomu Togawa (QCE, 2024)

QUBO Coefficient Dynamic Ratio Shrinking Method for Quantum Annealers. - Yuta Yachi; Masashi Tawada; Nozomu Togawa (QCE, 2024)

A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization. - Satoru Jimbo; Tatsuhiko Shirai; Nozomu Togawa; Masato Motomura; Kazushi Kawamura (IEEE Access, 2024)

Toward Practical Benchmarks of Ising Machines: A Case Study on the Quadratic Knapsack Problem. - Kentaro Ohno; Tatsuhiko Shirai; Nozomu Togawa (IEEE Access, 2024)

QUBO Formulation Using Sequence Pair With Search Space Restriction for Rectangle Packing Problem. - Akihisa Okada; Keisuke Otaki; Tadayoshi Matsumori; Hiroaki Yoshida; Kotaro Terada; Nozomu Togawa (IEEE Access, 2024)

Ising Machine Approach to the Lecturer-Student Assignment Problem. - Sora Tomita; Tatsuhiko Shirai; Nozomu Togawa (IEEE Access, 2024)

Foreword. - Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

An Anomalous Behavior Detection Method Utilizing IoT Power Waveform Shapes. - Kota Hisafuru; Kazunari Takasaki; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Ising-Machine-Based Solver for Constrained Graph Coloring Problems. - Soma Kawakami; Yosuke Mukasa; Siya Bao; Dema Ba; Junya Arai; Satoshi Yagi; Junji Teramoto; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Giving a Quasi-Initial Solution to Ising Machines by Controlling External Magnetic Field Coefficients. - Soma Kawakami; Kentaro Ohno; Dema Ba; Satoshi Yagi; Junji Teramoto; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

Hardware-Trojan Detection at Gate-Level Netlists Using a Gradient Boosting Decision Tree Model and Its Extension Using Trojan Probability Propagation. - Ryotaro Negishi; Tatsuki Kurihara; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

An Ising-Machine-Based Solver of Vehicle Routing Problem With Balanced Pick-Up. - Siya Bao; Masashi Tawada; Shu Tanaka; Nozomu Togawa (IEEE Trans. Consumer Electron., 2024)

Verification of Internal Memory Readout by Voltage Fault Attack on Automotive ECUs. - Ryusei Eda; Kota Hisafuru; Katsuhiko Sato; Yuya Adachi; Nozomu Togawa (ICCE, 2025)

Autonomous Hardware-Trojan Generation Method Using Reinforcement Learning for Random Forest-Based Hardware-Trojan Detection. - Yuka Ikegami; Kento Hasegawa; Seira Hidano; Kazuhide Fukushima; Nozomu Togawa (ICCE, 2025)

An Ising Machine-Based Hybrid Optimization Method Using Constraint Conversion and Correction. - Kinya Iwata; Masashi Tawada; Nozomu Togawa (ICCE, 2025)

Machine Learning-Based Estimation of Dynamic Travel Times between Points of Interest. - Shoma Kaji; Dai Kajimoto; Tatsuya Noguchi; Toshinori Takayama; Siya Bao; Nozomu Togawa (ICCE, 2025)

Shoe-Based PDR System for Two-Dimensional Tracking. - Dai Kajimoto; Yusuke Tanaka; Siya Bao; Nozomu Togawa (ICCE, 2025)

Solving Task-Select Problems Using a Quantum Annealer. - Koki Mita; Yuta Yachi; Keisuke Fukada; Nozomu Togawa (ICCE, 2025)

Performance Comparison of the LLM Models on LLM-Based Seed Generation Method for IoT Device Fuzzing. - Hibiki Nakanishi; Kento Hasegawa; Seira Hidano; Kazuhide Fukushima; Kazuo Hashimoto; Nozomu Togawa (ICCE, 2025)

SubQUBO Annealing Based on Efficient Binary Variable Selection for Combinatorial Optimization Problems with One-Hot Constraints. - Tatsuya Noguchi; Keisuke Fukada; Siya Bao; Nozomu Togawa (ICCE, 2025)

Personalized Course Selection Optimization Using QAOA. - Takeru Ota; Keisuke Fukada; Tatsuhiko Shirai; Nozomu Togawa (ICCE, 2025)

Searching Candidate Sequences for RNA Aptamers Using Quantum Computation. - Sora Tomita; Tatsuhiko Shirai; Michiaki Hamada; Tatsuo Adachi; Nozomu Togawa (ICCE, 2025)

Evaluation of Hardware-Trojan Detection by Ensemble Learning Model for Circuits Inserted with a Trojan by an Automated Framework. - Sho Yoshimi; Yuka Ikegami; Ryotaro Negishi; Kota Hisafuru; Nozomu Togawa (ICCE, 2025)

Anomalous IoT Behavior Detection by LSTM-Based Power Waveform Prediction. - Ryusei Eda; Nozomu Togawa (IoTBDS, 2025)

Automating the Assessment of Japanese Cyber-Security Technical Assessment Requirements Using Large Language Models. - Kento Hasegawa; Yuka Ikegami; Seira Hidano; Kazuhide Fukushima; Kazuo Hashimoto; Nozomu Togawa (IoTBDS, 2025)

Automated Test Input Generation Based on Web User Interfaces via Large Language Models. - Kento Hasegawa; Hibiki Nakanishi; Seira Hidano; Kazuhide Fukushima; Kazuo Hashimoto; Nozomu Togawa (IoTBDS, 2025)

Hybrid subQUBO Annealing With a Correction Process for Multi-Day Intermodal Trip Planning. - Tatsuya Noguchi; Keisuke Fukada; Siya Bao; Nozomu Togawa (IEEE Access, 2025)

Hybrid Iterative Annealing Method Using a Quantum Annealer and a Classical Computer and Its Evaluation. - Keisuke Fukada; Tatsuhiko Shirai; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

Linearizing Binary Optimization Problems Using Variable Posets for Ising Machines. - Kentaro Ohno; Nozomu Togawa (IEEE Trans. Emerg. Top. Comput., 2025)

Node-Wise Hardware Trojan Detection Based on Graph Learning. - Kento Hasegawa; Kazuki Yamashita; Seira Hidano; Kazuhide Fukushima; Kazuo Hashimoto; Nozomu Togawa (IEEE Trans. Computers, 2025)