Laygen - An evolutionary approach to automatic analog IC layout generation. - Nuno Lourenço 003; Nuno Horta (ICECS, 2005)

Automatic analog IC layout generation based on a evolutionary computation approach. - Nuno C. Lourenço; Nuno C. G. Horta (GECCO, 2007)

GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation. - Nuno Lourenço 003; Nuno Horta (GECCO, 2012)

LAYGEN II: automatic analog ICs layout generator based on a template approach. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta (GECCO, 2012)

Multi-port multi-terminal analog router based on an evolutionary optimization kernel. - Ricardo Martins 003; Nuno Lourenço 003; António Canelas; Nuno Horta (IEEE Congress on Evolutionary Computation, 2013)

A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis. - Frederico Rocha; Nuno Lourenço 003; Ricardo Povoa; Ricardo Martins 003; Nuno Horta (IEEE Congress on Evolutionary Computation, 2013)

Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel. - Frederico Rocha; Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta (DoCEIS, 2013)

Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners. - Ricardo Povoa; Nuno Lourenço 003; Nuno Horta; Rui Santos-Tavares; João Goes (VLSI-SoC, 2013)

LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures. - Ricardo Martins 003; Nuno Lourenço 003; António Canelas; Nuno Horta (DATE, 2014)

A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner. - Ricardo Povoa; Nuno Lourenço 003; Nuno Horta; Rui Santos-Tavares; João Goes (ICECS, 2014)

LC-VCO automatic synthesis using multi-objective evolutionary techniques. - Ricardo Povoa; Ricardo Lourenco; Nuno Lourenço 003; António Canelas; Ricardo Martins 003; Nuno Horta (ISCAS, 2014)

Electromigration-aware analog Router with multilayer multiport terminal structures. - Ricardo Martins 003; Nuno Lourenço 003; António Canelas; Nuno Horta (Integr., 2014)

Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction. - Nuno Lourenço 003; Ricardo Martins 003; Nuno Horta (DATE, 2015)

Extraction and application of wiring symmetry rules to route analog multiport terminals. - Ricardo Martins 003; Nuno Lourenço 003; António Canelas; Nuno Horta (ISCAS, 2015)

A voltage-combiners-biased amplifier with enhanced gain and speed using current starving. - Ricardo Povoa; Nuno Lourenço 003; Nuno Horta; João Goes (ISCAS, 2015)

Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta (Expert Syst. Appl., 2015)

Floorplan-aware analog IC sizing and optimization based on topological constraints. - Nuno Lourenço 003; António Canelas; Ricardo Povoa; Ricardo Martins 003; Nuno Horta (Integr., 2015)

Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach. - David Neves; Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta (DATE, 2016)

On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies. - Ricardo Martins 003; António Canelas; Nuno Lourenço 003; Nuno Horta (SMACD, 2016)

Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations. - António Canelas; Ricardo Martins 003; Ricardo Povoa; Nuno Lourenço 003; Nuno Horta (SMACD, 2016)

Automated analog IC design constraints generation for a layout-aware sizing approach. - Andre Ferreira; Nuno Lourenço 003; Ricardo Martins 003; Nuno Horta (SMACD, 2016)

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation. - Nuno Lourenço 003; Ricardo Martins 003; António Canelas; Ricardo Povoa; Nuno Horta (Integr., 2016)

Current-flow and current-density-aware multi-objective optimization of analog IC placement. - Ricardo Martins 003; Ricardo Povoa; Nuno Lourenço 003; Nuno Horta (Integr., 2016)

Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer. - Mrinalinee Pandey; António Canelas; Ricardo Póvoa; Jorge Alves Torres; João Costa Freire; Nuno Lourenço 003; Nuno Horta (Integr., 2016)

Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques. - Ricardo Povoa; Ivan Bastos; Nuno Lourenço 003; Nuno Horta (Integr., 2016)

Automatic technology migration of analog IC designs using generic cell libraries. - Jose Cachaco; Nuno Machado; Nuno Lourenço 003; Jorge Guilherme; Nuno Horta (DATE, 2017)

Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing. - António Canelas; Ricardo Martins 003; Ricardo Povoa; Nuno Lourenço 003; Nuno Horta (DATE, 2017)

New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization. - Nuno C. Lourenço; Ricardo Martins 003; Ricardo Povoa; António Canelas; Nuno Horta; Fábio Passos; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2017)

Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks. - Ricardo Martins 003; Nuno C. Lourenço; Ricardo Povoa; António Canelas; Nuno Horta; Fábio Passos; Rafael Castro-López; Elisenda Roca; Francisco V. Fernández 001 (SMACD, 2017)

Systematic design of a voltage controlled oscillator using a layout-aware approach. - Fábio Passos; Elisenda Roca; Rafael Castro-López; Francisco V. Fernández 001; Ricardo Martins 003; Nuno C. Lourenço; Ricardo Povoa; António Canelas; Nuno C. G. Horta (SMACD, 2017)

Stochastic-based placement template generator for analog IC layout-aware synthesis. - Ricardo Martins 003; Nuno Lourenço 003; António Canelas; Nuno Horta (Integr., 2017)

Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel. - Tiago Pessoa; Nuno Lourenço 003; Ricardo Martins 003; Ricardo Povoa; Nuno Horta (DATE, 2018)

Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (SMACD, 2018)

On the Exploration of Promising Analog IC Designs via Artificial Neural Networks. - Nuno Lourenço 003; Joao Rosa; Ricardo Martins 003; Helena Aidos; António Canelas; Ricardo Povoa; Nuno Horta (SMACD, 2018)

A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications. - António Canelas; Ricardo Povoa; Ricardo M. F. Martins; Nuno Lourenço 003; Jorge Guilherme; Nuno Horta (SMACD, 2018)

Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. - Fábio Passos; Ricardo Martins 003; Nuno C. Lourenço; Elisenda Roca; Rafael Castro-López; Ricardo Povoa; António Canelas; Nuno Horta; Francisco V. Fernández 001 (SMACD, 2018)

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. - Fábio Passos; Ricardo Martins 003; Nuno Lourenço 003; Elisenda Roca; Ricardo Povoa; António Canelas; Rafael Castro-López; Nuno Horta; Francisco V. Fernández 001 (Integr., 2018)

Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement. - Ricardo Povoa; Nuno Lourenço 003; Ricardo Martins 003; António Canelas; Nuno Cavaco Gomes Horta; João Goes (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving. - Ricardo Povoa; Nuno Lourenço 003; Ricardo Martins 003; António Canelas; Nuno Horta; João Goes (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization. - Nuno Lourenço 003; Ricardo Martins 003; António Canelas; Ricardo Póvoa; Nuno Horta; Emmanuel Moutaye (SMACD, 2019)

Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (SMACD, 2019)

On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects. - Ricardo Martins 003; Nuno Lourenço 003; Ricardo Póvoa; Nuno Horta (SMACD, 2019)

Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing. - Nuno Lourenço 003; Engin Afacan; Ricardo Martins 003; Fábio Passos; António Canelas; Ricardo Póvoa; Nuno Horta; Günhan Dündar (SMACD, 2019)

Artificial Neural Networks as an Alternative for Automatic Analog IC Placement. - Daniel Guerra; António Canelas; Ricardo Póvoa; Nuno Horta; Nuno Lourenço 003; Ricardo Martins 003 (SMACD, 2019)

A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers. - Ricardo Póvoa; António Canelas; Ricardo Martins 003; Nuno Horta; Nuno Lourenço 003; João Goes (SMACD, 2019)

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. - Ricardo Martins 003; Nuno Lourenço 003; Fábio Passos; Ricardo Povoa; António Canelas; Elisenda Roca; Rafael Castro-López; Javier J. Sieiro; Francisco V. Fernández 001; Nuno Horta (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Analog IC Placement Generation via Neural Networks from Unlabeled Data - António Gusmão 001; Nuno Horta; Nuno Lourenço 003; Ricardo Martins 003 (Springer, 2020)

Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender. - António Gusmão 001; Fábio Passos; Ricardo Póvoa; Nuno Horta; Nuno Lourenço 003; Ricardo Martins 003 (ISCAS, 2020)

Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology. - Fábio Passos; Elisenda Roca; Ricardo Martins 003; Nuno Lourenço 003; Saiyd Ahyoune; Javier J. Sieiro; Rafael Castro-López; Nuno Horta; Francisco V. Fernández 001 (IEEE Access, 2020)

A new family of CMOS inverter-based OTAs for biomedical and healthcare applications. - Ricardo Póvoa; António Canelas; Ricardo Martins 003; Nuno Horta; Nuno Lourenço 003; João Goes (Integr., 2020)

Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications. - Ricardo Póvoa; Richa Arya; António Canelas; Fábio Passos; Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta (Microelectron. J., 2020)

FUZYE: A Fuzzy c-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms. - António Canelas; Ricardo Póvoa; Ricardo Martins 003; Nuno Lourenço 003; Jorge Guilherme; João Paulo Carvalho 001; Nuno Horta (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Shenke Zhong; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications. - Ricardo Póvoa; Nuno Lourenço 003; Ricardo Martins 003; António Canelas; Nuno Horta; João Goes (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement. - António Gusmão 001; Nuno Horta; Nuno Lourenço 003; Ricardo Martins 003 (DAC, 2021)

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. - António Canelas; Fábio Passos; Nuno Lourenço 003; Ricardo Martins 003; Elisenda Roca; Rafael Castro-López; Nuno Horta; Francisco V. Fernández 001 (IEEE Access, 2021)

In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization. - Luís Mendes; João Caldinhas Vaz; Fábio Passos; Nuno Lourenço 003; Ricardo Martins 003 (IEEE Access, 2021)

Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing. - Ricardo Martins 003; Nuno Lourenço 003; Ricardo Póvoa; Nuno Horta (Eng. Appl. Artif. Intell., 2021)

Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test. - Engin Afacan; Nuno Lourenço 003; Ricardo Martins 003; Günhan Dündar (Integr., 2021)

Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS. - Luís Mendes; João Caldinhas Vaz; Fábio Passos; Nuno Lourenço 003; Ricardo Martins 003 (ISCAS, 2022)

A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications. - Fábio Passos; Rafael Vieira; António Canelas; Ricardo Póvoa; Nuno Lourenço 003; Nuno Horta; Jorge Guilherme (ISCAS, 2022)

Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs. - Pedro Vaz; António Gusmão 001; Nuno Horta; Nuno Lourenço 003; Ricardo Martins 003 (ISCAS, 2022)

Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/°C Temperature Coefficient. - Nuno Lourenço 003; Fábio Passos; Rafael Vieira; Ricardo Martins 003; Nuno Horta; Jorge Guilherme; Ricardo Póvoa (SMACD, 2022)

ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage. - Pedro Alves; António Gusmão 001; Nuno Horta; Nuno Lourenço 003; Ricardo Martins 003 (SMACD, 2022)

Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors. - João Domingues; António Gusmão 001; Nuno Horta; Nuno Lourenço 003; Ricardo Martins 003 (SMACD, 2022)

Machine Learning Approaches for Transformer Modeling. - Fábio Passos; Nuno C. Lourenço; Ricardo Martins 003; Elisenda Roca; Rafael Castro-López; Nuno Horta; Francisco V. Fernández 001 (SMACD, 2022)

Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling. - Rafael Vieira; Fábio Passos; Ricardo Povoa; Ricardo Martins 003; Nuno Horta; Jorge Guilherme; Nuno Lourenço 003 (SMACD, 2022)

DeepPlacer: A custom integrated OpAmp placement tool using deep models. - António Gusmão 001; Ricardo Póvoa; Nuno Horta; Nuno Lourenço 003; Ricardo Martins 003 (Appl. Soft Comput., 2022)

Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models. - António Paiva Lapas de Gusmão; Nuno Cavaco Gomes Horta; Nuno Calado Correia Lourenço; Ricardo Miguel Ferreira Martins (Expert Syst. Appl., 2022)

Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models. - Fábio Passos; Nuno Lourenço 003; Luís Mendes; Ricardo Martins 003; João Caldinhas Vaz; Nuno Horta (ASP-DAC, 2023)

An ANN-Based Approach to the Modelling and Simulation of Analogue Circuits. - André Amaral; António Gusmão 001; Rafael Vieira; Ricardo Martins 003; Nuno Horta; Nuno Lourenço 003 (SMACD, 2023)

A 23.5-32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology. - Fábio Passos; Nuno Lourenço 003; Luís Mendes; Ricardo Martins 003; João Caldinhas Vaz; Nuno Horta (SMACD, 2023)

Design Space Exploration of Single-Stage OTAs towards an Ultra-Low-Power LNA for ECG Signals. - Rafael Vieira; Ricardo Martins 003; Nuno Horta; Nuno Lourenço 003 (SMACD, 2023)

Analog Integrated Circuit Routing Techniques: An Extensive Review. - Ricardo M. F. Martins; Nuno Lourenço 003 (IEEE Access, 2023)

Behavioral Analysis of Noise and Bandwidth Specifications of Heartbeat Detection Circuits for Ultra Low Power Devices. - Rafael Vieira; Fábio Passos; Ricardo Martins 003; Nuno Horta; Nuno Lourenço 003 (IEEE Access, 2023)

Solving the Inverse Problem of Analog Integrated Circuit Sizing with Diffusion Models. - Pedro Eid; Filipe Azevedo 001; Ricardo Martins 003; Nuno Lourenço 003 (SMACD, 2024)

Ponderous: A Performance-driven Analog IC Placement Optimizer Leveraged by a ML Pipeline. - Ricardo Martins 003; António Gusmão 001; Rafael Vieira; Fábio Passos; Nuno Lourenço 003; Nuno Horta (SMACD, 2024)

Low-Power 9.6-11GHz and 10.8-12GHz VCOs Designed for a 2.5/5GHz TRx using High-Q Inductors Synthesized with ML Techniques. - Fábio Passos; Ricardo M. F. Martins; Nuno Lourenço 003 (SMACD, 2024)

Effective Routing Probability Maps via Convolutional Neural Networks for Analog IC Layout Automation. - Diogo Peneda; Filipe Azevedo 001; Nuno Lourenço 003; Nuno Horta; Ricardo Martins 003 (SMACD, 2024)

A 25 nW Heartbeat Monitoring Circuit for Wearable Applications in CMOS 65nm. - Rafael Vieira; Seyedehsomayeh Hatefinasab; Ricardo Martins 003; Nuno Horta; Nuno Lourenço 003 (SMACD, 2024)

An Efficient Performance-Driven Analog IC Placement Optimizer Via Extremely Randomized Tree-Based Post-Layout Performance Regressors. - Ricardo Martins; Nuno Lourenço 003 (VLSI-SoC, 2024)

Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks - A Tutorial Brief. - Gustavo Liñán Cembrano; Nuno Lourenço 003; Nuno Horta; José M. de la Rosa 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Fully CMOS Boost Converter Operating at 2.65 GHz for Photovoltaic Energy Harvesting. - Pedro Mendonça dos Santos; Ricardo A. Marques Lameirinhas; Catarina P. Correia V. Bernardo; João Paulo N. Torres 001; António Serralheiro; Rafael Vieira; Nuno Lourenço 003 (IEEE Access, 2025)

Comprehensive application of denoising diffusion probabilistic models towards the automation of analog integrated circuit sizing. - Filipe Parrado de Azevedo; Nuno Calado Correia Lourenço; Ricardo Miguel Ferreira Martins (Expert Syst. Appl., 2025)