From Instruction Traces to Specialized Reconfigurable Arrays. - João Bispo; Nuno Miguel Cardanha Paulino; João M. P. Cardoso; João Canas Ferreira (ReConFig, 2011)

Architecture for Transparent Binary Acceleration of Loops with Memory Accesses. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João M. P. Cardoso (ARC, 2013)

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units. - João Bispo; Nuno Miguel Cardanha Paulino; João M. P. Cardoso; João Canas Ferreira (Int. J. Reconfigurable Comput., 2013)

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems. - João Bispo; Nuno Miguel Cardanha Paulino; João M. P. Cardoso; João Canas Ferreira (IEEE Trans. Ind. Informatics, 2013)

Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João Manuel Paiva Cardoso (ISPA, 2014)

Transparent acceleration of program execution using reconfigurable hardware. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João Bispo; João M. P. Cardoso (DATE, 2015)

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João M. P. Cardoso (ACM Trans. Reconfigurable Technol. Syst., 2015)

Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration - Nuno Miguel Cardanha Paulino (2016)

On Coding Techniques for Targeting FPGAs via OpenCL. - Nuno Paulino 001; Luís Reis 001; João M. P. Cardoso (PARCO, 2017)

Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João M. P. Cardoso (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Dynamic Partial Reconfiguration of Customized Single-Row Accelerators. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João M. P. Cardoso (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. - Nuno Paulino 001; João Canas Ferreira; João Bispo; João M. P. Cardoso (FPL, 2020)

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets. - Nuno Paulino 001; João Canas Ferreira; João M. P. Cardoso (IEEE Access, 2020)

Evaluating a Novel Bluetooth 5.1 AoA Approach for Low-Cost Indoor Vehicle Tracking via Simulation. - Nuno Paulino 001; Luís M. Pessoa; André Branquinho; Edgar Gonçalves (EuCNC/6G Summit, 2021)

On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators. - Tiago Santos; Nuno Paulino 001; João Bispo; João M. P. Cardoso; João Canas Ferreira (FPT, 2021)

FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example. - Pedro Filipe Silva; João Bispo; Nuno Paulino 001 (FPT, 2021)

Building Beyond HLS: Graph Analysis and Others. - Pedro Filipe Silva; João Bispo; Nuno Miguel Cardanha Paulino (CoRR, 2021)

Augmentation of base classifier performance via HMMs on a handwritten character data set. - Hélder Campos; Nuno Paulino 001 (CoRR, 2021)

Multiple target tracking with interaction using an MCMC MRF Particle Filter. - Hélder F. S. Campos; Nuno Paulino 001 (CoRR, 2021)

Optimizing Packet Reception Rates for Low Duty-Cycle BLE Relay Nodes. - Nuno Miguel Cardanha Paulino; Luís M. Pessoa; André Branquinho; Rafael Tavares; Igor Ferreira (CoRR, 2021)

A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA. - Luís Miguel Sousa; Nuno Miguel Cardanha Paulino; João Canas Ferreira; João Bispo (CoRR, 2021)

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey. - Nuno Paulino 001; João Canas Ferreira; João M. P. Cardoso (ACM Comput. Surv., 2021)

A Binary Translation Framework for Automated Hardware Generation. - Nuno Paulino 001; João Bispo; João Canas Ferreira; João M. P. Cardoso (IEEE Micro, 2021)

Design and Experimental Evaluation of a Bluetooth 5.1 Antenna Array for Angle-of-Arrival Estimation. - Nuno Paulino 001; Luís M. Pessoa; André Branquinho; Edgar Gonçalves (CSNDSP, 2022)

A Batch of Integer Data Sets for Clustering Algorithms. - Nuno Paulino 001 (IEEE DataPort, 2022)

A Dataset of Phase Samples using an 8-Element Uniform Circular Antenna Array and a Bluetooth Low Energy 5.1 Nordic nRF52811 Based Receiver. - Nuno Paulino 001 (IEEE DataPort, 2022)

Retargeting Applications for Heterogeneous Systems with the Tribble Source-to-Source Framework. - Luís Miguel Sousa; João Bispo; Nuno Paulino 001 (PACT, 2023)

Enhancing NLoS RIS-Aided Localization with Optimization and Machine Learning. - Rafael A. Aguiar; Nuno Paulino 001; Luís M. Pessoa (GLOBECOM (Workshops), 2023)

Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper). - João Bispo; Nuno Paulino 001; Luís Miguel Sousa (PARMA-DITAM, 2023)

Self-Localization via Circular Bluetooth 5.1 Antenna Array Receiver. - Nuno Paulino 001; Luís M. Pessoa (IEEE Access, 2023)

A DSL and MLIR Dialect for Streaming and Vectorisation. - Manuel Cerqueira da Silva; Luís Miguel Sousa; Nuno Paulino 001; João Bispo (ARC, 2024)

A Deep Learning Approach in RIS-based Indoor Localization. - Rafael A. Aguiar; Nuno Paulino 001; Luís M. Pessoa (EuCNC/6G Summit, 2024)

CONVERGE: A Vision-Radio Research Infrastructure Towards 6G and Beyond. - Filipe B. Teixeira; Manuel Ricardo 001; André Coelho; Hélder P. Oliveira; Paula Viana; Nuno Paulino 001; Helder Fontes; Paulo Marques; Rui Campos; Luís M. Pessoa (EuCNC/6G Summit, 2024)

SpecRF-Posture: Exploring Specular Reflections for Human Posture Recognition. - Mariana Oliveira; Francisco M. Ribeiro; Nuno Paulino 001; Okan Yurduseven; Luís M. Pessoa (MeditCom, 2024)

Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study. - Miguel Henriques; João Bispo; Nuno Paulino 001 (RAPIDO@HiPEAC, 2024)

Vision-Radio Experimental Infrastructure Architecture Towards 6G. - Filipe B. Teixeira; Manuel Ricardo 001; André Coelho; Hélder P. Oliveira; Paula Viana; Nuno Paulino 001; Helder Fontes; Paulo Marques; Rui Campos; Luís M. Pessoa (CoRR, 2024)

Human Activity Recognition with a Reconfigurable Intelligent Surface for Wi-Fi 6E. - Nuno Paulino 001; Mariana Oliveira; Francisco M. Ribeiro; Luís Outeiro; Luís M. Pessoa (EuCNC/6G Summit, 2025)

SIMD Acceleration of Matrix-Vector Operations on RISC-V for Variable Precision Neural Networks. - Gonzalo Salinas; Guilherme Sequeira; Alfonso Rodríguez 002; João Bispo; Nuno Paulino 001 (IPDPS (Workshops), 2025)