Smart Memories: a modular reconfigurable architecture. - Ken Mai; Tim Paaske; Nuwan Jayasena; Ron Ho; William J. Dally; Mark Horowitz (ISCA, 2000)

Merrimac: Supercomputing with Streams. - William J. Dally; Francois Labonte; Abhishek Das; Pat Hanrahan; Jung Ho Ahn; Jayanth Gummaraju; Mattan Erez; Nuwan Jayasena; Ian Buck; Timothy J. Knight; Ujval J. Kapasi (SC, 2003)

Stream Register Files with Indexed Access. - Nuwan Jayasena; Mattan Erez; Jung Ho Ahn; William J. Dally (HPCA, 2004)

Fault Tolerance Techniques for the Merrimac Streaming Supercomputer. - Mattan Erez; Nuwan Jayasena; Timothy J. Knight; William J. Dally (SC, 2005)

Load balancing in a changing world: dealing with heterogeneity and performance variability. - Michael Boyer; Kevin Skadron; Shuai Che; Nuwan Jayasena (Conf. Computing Frontiers, 2013)

A new perspective on processing-in-memory architecture design. - Dong Ping Zhang; Nuwan Jayasena; Alexander Lyashevsky; Joseph L. Greathouse; Mitesh R. Meswani; Mark Nutter; Mike Ignatowski (MSPC@PLDI, 2013)

Improving Node-Level MapReduce Performance Using Processing-in-Memory Technologies. - Mahzabeen Islam; Marko Scrbak; Krishna M. Kavi; Mike Ignatowski; Nuwan Jayasena (Euro-Par Workshops (2), 2014)

TOP-PIM: throughput-oriented programmable processing in memory. - Dong Ping Zhang; Nuwan Jayasena; Alexander Lyashevsky; Joseph L. Greathouse; Lifan Xu; Michael Ignatowski (HPDC, 2014)

Managing DRAM Latency Divergence in Irregular GPGPU Applications. - Niladrish Chatterjee; Mike O'Connor; Gabriel H. Loh; Nuwan Jayasena; Rajeev Balasubramonian (SC, 2014)

A comparison of core power gating strategies implemented in modern hardware. - Manish Arora; Srilatha Manne; Yasuko Eckert; Indrani Paul; Nuwan Jayasena; Dean M. Tullsen (SIGMETRICS, 2014)

Processing-in-Memory: Exploring the Design Space. - Marko Scrbak; Mahzabeen Islam; Krishna M. Kavi; Mike Ignatowski; Nuwan Jayasena (ARCS, 2015)

Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems. - Manish Arora; Srilatha Manne; Indrani Paul; Nuwan Jayasena; Dean M. Tullsen (HPCA, 2015)

GPGPU performance and power estimation using machine learning. - Gene Y. Wu; Joseph L. Greathouse; Alexander Lyashevsky; Nuwan Jayasena; Derek Chiou (HPCA, 2015)

Achieving Exascale Capabilities through Heterogeneous Computing. - Michael J. Schulte; Mike Ignatowski; Gabriel H. Loh; Bradford M. Beckmann; William C. Brantley; Sudhanva Gurumurthi; Nuwan Jayasena; Indrani Paul; Steven K. Reinhardt; Gregory Rodgers (IEEE Micro, 2015)

Prefetching Techniques for Near-memory Throughput Processors. - Reena Panda; Yasuko Eckert; Nuwan Jayasena; Onur Kayiran; Michael Boyer; Lizy Kurian John (ICS, 2016)

HADM: Hybrid Analysis for Detection of Malware. - Lifan Xu; Dong Ping Zhang; Nuwan Jayasena; John Cavazos (IntelliSys (2), 2016)

Fine-Grained Task Migration for Graph Algorithms Using Processing in Memory. - Paula Aguilera; Dong Ping Zhang; Nam Sung Kim; Nuwan Jayasena (IPDPS Workshops, 2016)

Analytical Study on Bandwidth Efficiency of Heterogeneous Memory Systems. - Amin Farmahini Farahani; David Roberts; Nuwan Jayasena (MEMSYS, 2016)

Horton Tables: Fast Hash Tables for In-Memory Data-Intensive Computing. - Alex D. Breslow; Dong Ping Zhang; Joseph L. Greathouse; Nuwan Jayasena; Dean M. Tullsen (USENIX ATC, 2016)

Near-Memory Data Services. - Babak Falsafi; Mircea Stan; Kevin Skadron; Nuwan Jayasena; Yunji Chen; Jinhua Tao; Ravi Nair; Jaime H. Moreno; Naveen Muralimanohar; Karthikeyan Sankaralingam; Cristian Estan (IEEE Micro, 2016)

HBM-Resident Prefetching for Heterogeneous Memory System. - Mahzabeen Islam; Krishna M. Kavi; Mitesh R. Meswani; Soumik Banerjee; Nuwan Jayasena (ARCS, 2017)

DVFS Space Exploration in Power Constrained Processing-in-Memory Systems. - Marko Scrbak; Joseph L. Greathouse; Nuwan Jayasena; Krishna M. Kavi (ARCS, 2017)

MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories. - Andreas Prodromou; Mitesh R. Meswani; Nuwan Jayasena; Gabriel H. Loh; Dean M. Tullsen (HPCA, 2017)

CODA: Enabling Co-location of Computation and Data for Near-Data Processing. - Hyojong Kim; Ramyad Hadidi; Lifeng Nai; Hyesoon Kim; Nuwan Jayasena; Yasuko Eckert; Onur Kayiran; Gabriel H. Loh (CoRR, 2017)

Exploring the Processing-in-Memory design space. - Marko Scrbak; Mahzabeen Islam; Krishna M. Kavi; Mike Ignatowski; Nuwan Jayasena (J. Syst. Archit., 2017)

RegMutex: Inter-Warp GPU Register Time-Sharing. - Farzad Khorasani; Hodjat Asghari Esfeden; Amin Farmahini Farahani; Nuwan Jayasena; Vivek Sarkar (ISCA, 2018)

Morton Filters: Faster, Space-Efficient Cuckoo Filters via Biasing, Compression, and Decoupled Logical Sparsity. - Alexander Dodd Breslow; Nuwan Jayasena (Proc. VLDB Endow., 2018)

CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems. - Hyojong Kim; Ramyad Hadidi; Lifeng Nai; Hyesoon Kim; Nuwan Jayasena; Yasuko Eckert; Onur Kayiran; Gabriel H. Loh (ACM Trans. Archit. Code Optim., 2018)

Co-ML: a case for collaborative ML acceleration using near-data processing. - Shaizeen Aga; Nuwan Jayasena; Mike Ignatowski (MEMSYS, 2019)

SeqPoint: Identifying Representative Iterations of Sequence-Based Neural Networks. - Suchita Pati; Shaizeen Aga; Matthew D. Sinclair; Nuwan Jayasena (ISPASS, 2020)

Memory Performance Optimization. - Nuwan Jayasena (IA3@SC, 2020)

Morton filters: fast, compressed sparse cuckoo filters. - Alex D. Breslow; Nuwan Jayasena (VLDB J., 2020)

Demystifying BERT: Implications for Accelerator Design. - Suchita Pati; Shaizeen Aga; Nuwan Jayasena; Matthew D. Sinclair (CoRR, 2021)

Demystifying BERT: System Design Implications. - Suchita Pati; Shaizeen Aga; Nuwan Jayasena; Matthew D. Sinclair (IISWC, 2022)

Tale of Two Cs: Computation vs. Communication Scaling for Future Transformers on Future Hardware. - Suchita Pati; Shaizeen Aga; Mahzabeen Islam; Nuwan Jayasena; Matthew D. Sinclair (IISWC, 2023)

A Research Retrospective on AMD's Exascale Computing Journey. - Gabriel H. Loh; Michael J. Schulte; Mike Ignatowski; Vignesh Adhinarayanan; Shaizeen Aga; Derrick Aguren; Varun Agrawal; Ashwin M. Aji; Johnathan Alsop; Paul T. Bauman; Bradford M. Beckmann; Majed Valad Beigi; et al. (ISCA, 2023)

Computation vs. Communication Scaling for Future Transformers on Future Hardware. - Suchita Pati; Shaizeen Aga; Mahzabeen Islam; Nuwan Jayasena; Matthew D. Sinclair (CoRR, 2023)

Inclusive-PIM: Hardware-Software Co-design for Broad Acceleration on Commercial PIM Architectures. - Johnathan Alsop; Shaizeen Aga; Mohamed Assem Ibrahim; Mahzabeen Islam; Andrew McCrabb; Nuwan Jayasena (CoRR, 2023)

T3: Transparent Tracking & Triggering for Fine-grained Overlap of Compute & Collectives. - Suchita Pati; Shaizeen Aga; Mahzabeen Islam; Nuwan Jayasena; Matthew D. Sinclair (ASPLOS (2), 2024)

PIM-Potential: Broadening the Acceleration Reach of PIM Architectures. - Johnathan Alsop; Shaizeen Aga; Mohamed Assem Ibrahim; Mahzabeen Islam; Nuwan Jayasena; Andrew McCrabb (MEMSYS, 2024)

Global Optimizations & Lightweight Dynamic Logic for Concurrency. - Suchita Pati; Shaizeen Aga; Nuwan Jayasena; Matthew D. Sinclair (CoRR, 2024)

Concurrent PIM and Load/Store Servicing in PIM-Enabled Memory. - Sudhanshu Gupta 002; Niti Madan; Sooraj Puthoor; Nuwan Jayasena; Sandhya Dwarkadas (ISPASS, 2025)

GOLDYLOC: Global Optimizations & Lightweight Dynamic Logic for Concurrency. - Suchita Pati; Shaizeen Aga; Nuwan Jayasena; Matthew D. Sinclair (ACM Trans. Archit. Code Optim., 2025)