Design of controller for L2 cache mapped in Tezzaron stacked DRAM. - Nyunyi M. Tshibangu; Paul D. Franzon; Eric Rotenberg; William Rhett Davis (3DIC, 2013)

Rationale for a 3D heterogeneous multi-core processor. - Eric Rotenberg; Brandon H. Dwiel; Elliott Forbes; Zhenqian Zhang; Randy Widialaksono; Rangeen Basu Roy Chowdhury; Nyunyi M. Tshibangu; Steve Lipa; W. Rhett Davis; Paul D. Franzon (ICCD, 2013)