A Scaling Scheme and Optimization Methodology for Deep Sub-Micron Interconnect. - Soo-Young Oh; Khalid Rahmat; O. Sam Nakagawa; John Moll (ICCD, 1996)

Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect. - Norman Chang; Valery Kanevsky; O. Sam Nakagawa; Khalid Rahmat; Soo-Young Oh (ICCD, 1997)

An efficient inductance modeling for on-chip interconnects. - Lei He 001; Norman Chang; Shen Lin; O. Sam Nakagawa (CICC, 1999)

Clocktree RLC Extraction with Efficient Inductance Modeling. - Norman Chang; Shen Lin; O. Sam Nakagawa; Weize Xie; Lei He 001 (DATE, 2000)

Quick On-Chip Self- and Mutual-Inductance Screen. - Shen Lin; Norman Chang; O. Sam Nakagawa (ISQED, 2000)

Full Chip Thermal Simulation. - Zhiping Yu; Dan Yergeau; Robert W. Dutton; O. Sam Nakagawa; Norman Chang; Shen Lin; Weize Xie (ISQED, 2000)

Ramp Up/Down Functional Unit to Reduce Step Power. - Zhenyu Tang; Norman Chang; Shen Lin; Weize Xie; O. Sam Nakagawa; Lei He 001 (PACS, 2000)

Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. - Yu Cao 001; Xuejue Huang; Chenming Hu; Norman Chang; Shen Lin; O. Sam Nakagawa; Weize Xie (ISQED, 2001)

Instruction Prediction for Step Power Reduction. - Zhenyu Tang; Lei He 001; Norman Chang; Shen Lin; Weize Xie; O. Sam Nakagawa (ISQED, 2001)

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. - Yu Cao 001; Xuejue Huang; N. H. Chang; Shen Lin; O. Sam Nakagawa; Weize Xie; Dennis Sylvester; Chenming Hu (IEEE Trans. Very Large Scale Integr. Syst., 2002)