Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks? - Ognjen Glamocanin; Louis Coulon; Francesco Regazzoni 001; Mirjana Stojilovic (DATE, 2020)

Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs. - Ognjen Glamocanin; Louis Coulon; Francesco Regazzoni 001; Mirjana Stojilovic (FPGA, 2020)

Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks. - Ognjen Glamocanin; Dina G. Mahmoud; Francesco Regazzoni 001; Mirjana Stojilovic (DATE, 2021)

Improving First-Order Threshold Implementations of SKINNY. - Andrea Caforio; Daniel Collins 001; Ognjen Glamocanin; Subhadeep Banik (IACR Cryptol. ePrint Arch., 2021)

The Side-Channel Metric Cheat Sheet. - Kostas Papagiannopoulos; Ognjen Glamocanin; Melissa Azouaoui; Dorian Ros; Francesco Regazzoni 001; Mirjana Stojilovic (IACR Cryptol. ePrint Arch., 2022)

Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs. - Ognjen Glamocanin; Hajira Bazaz; Mathias Payer; Mirjana Stojilovic (DATE, 2023)

Active Wire Fences for Multitenant FPGAs. - Ognjen Glamocanin; Andela Kostic; Stasa Kostic; Mirjana Stojilovic (DDECS, 2023)

The Side-channel Metrics Cheat Sheet. - Kostas Papagiannopoulos; Ognjen Glamocanin; Melissa Azouaoui; Dorian Ros; Francesco Regazzoni 001; Mirjana Stojilovic (ACM Comput. Surv., 2023)

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks. - David Spielmann; Ognjen Glamocanin; Mirjana Stojilovic (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023)

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs. - Ognjen Glamocanin; Shashwat Shrivastava; Jinwei Yao; Nour Ardo; Mathias Payer; Mirjana Stojilovic (J. Hardw. Syst. Secur., 2023)