A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow. - Prashanth Mohan; Oguz Atli; Onur O. Kibar; Ken Mai (FPGA, 2020)

Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion. - Prashanth Mohan; Oguz Atli; Joseph Sweeney; Onur O. Kibar; Larry T. Pileggi; Ken Mai (DATE, 2021)

Top-down Physical Design of Soft Embedded FPGA Fabrics. - Prashanth Mohan; Oguz Atli; Onur O. Kibar; V. Mohammed Zackriya; Larry T. Pileggi; Ken Mai (FPGA, 2021)

Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture. - Graham Gobieski; Ahmet Oguz Atli; Kenneth Mai; Brandon Lucia; Nathan Beckmann (ISCA, 2021)

MANIC: A $19 mu mathrm{W}$ @ 4MHz, 256 MOPS/mW, RISC-V microcontroller with embedded MRAM main memory and vector-dataflow co-processor in 22nm bulk finFET CMOS. - Graham Gobieski; Oguz Atli; Cagri Erbagci; Ken Mai; Nathan Beckmann; Brandon Lucia (ISCAS, 2023)

A Soft Error Tolerant Flip-Flop for eFPGA Configuration Hardening in 22nm FinFET Process. - Prashanth Mohan; Siddharth Das; Oguz Atli; Josh Joffrion; Ken Mai (DATE, 2025)