On Multivalued Multithreshold Networks Composed of Conventional Threshold Elements. - Okihiko Ishizuka (IEEE Trans. Computers, 1977)

On Design of Multiple-Valued Static Random-Access-Memory. - Okihiko Ishizuka; Zheng Tang; Hiroki Matsumoto (ISMVL, 1990)

Synthesis of Current-Mode Pass Transistor Networks. - Okihiko Ishizuka; Hiroshi Takarabe; Zheng Tang; Hiroki Matsumoto (ISMVL, 1991)

Algorithm and Implementation of a Learning Multiple-Valued Logic Network. - Qixin Cao; Okihiko Ishizuka; Zheng Tang; Hiroki Matsumoto (ISMVL, 1993)

Algebraic Properties of a Learning Multiple-Valued Logic Network. - Zheng Tang; Okihiko Ishizuka; Qixin Cao; Hiroki Matsumoto (ISMVL, 1993)

A Self-Calibrating A/D Converter Using T-Model Neural Network. - Zheng Tang; Yuichi Shirata; Okihiko Ishizuka; Koichi Tanno (ISCAS, 1995)

Learning Multiple-Valued Logic Networks Based on Back Propagation. - Zheng Tang; Okihiko Ishizuka; Koichi Tanno (ISMVL, 1995)

VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products. - Okihiko Ishizuka; Akihiro Ohta; Koichi Tanno; Zheng Tang; Dwi Handoko (ISMVL, 1997)

Multiple-Valued Immune Network Model and Its Simulations. - Zheng Tang; Takayuki Yamaguchi; Koichi Tashima; Okihiko Ishizuka; Koichi Tanno (ISMVL, 1997)

Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits. - Jing Shen; Koichi Tanno; Okihiko Ishizuka; Zheng Tang (ISMVL, 1998)

A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications. - Zheng Tang; Okihiko Ishizuka (IEEE Trans. Computers, 1998)

Down Literal Circuit with Neuron-MOS Transistors and Its Applications. - Jing Shen; Koichi Tanno; Okihiko Ishizuka (ISMVL, 1999)

Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. - Jing Shen; Motoi Inaba; Koichi Tanno; Okihiko Ishizuka (ISMVL, 2000)

Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions. - Makoto Syuto; Jing Shen; Koichi Tanno; Okihiko Ishizuka (ISMVL, 2000)

Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators. - Motoi Inaba; Koichi Tanno; Okihiko Ishizuka (ISMVL, 2001)

An immune network with interactions between B cells for pattern recognition. - Koichi Tashima; Zheng Tang; Okihiko Ishizuka; Koichi Tanno (Syst. Comput. Jpn., 2001)

Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. - Motoi Inaba; Koichi Tanno; Okihiko Ishizuka (ISMVL, 2002)

Analog Inverter with Neuron-MOS Transistors and Its Application. - Motoi Inaba; Koichi Tanno; Okihiko Ishizuka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Low-Power and Wide-Input Range Voltage Controlled Linear Variable Resistor Using an FG-MOSFET and Its Application. - Muneo Kushima; Koichi Tanno; Okihiko Ishizuka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Wide-Input Range Variable Resistor Circuit Using an FG-MOSFET. - Muneo Kushima; Koichi Tanno; Okihiko Ishizuka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Wide Input-Range Four-Quadrant Analog Multiplier Using Floating-Gate MOSFET's. - Dasong Zhu; Koichi Tanno; Okihiko Ishizuka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Combiner-Based MOS OTAs. - Koichi Tanno; Kenya Kondo; Okihiko Ishizuka; Takako Toyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit. - Koichi Tanno; Kiminobu Sato; Hisashi Tanaka; Okihiko Ishizuka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits. - Motoi Inaba; Koichi Tanno; Hiroki Tamura; Okihiko Ishizuka (IEICE Trans. Inf. Syst., 2010)