Hardware emulation board based on FPGAs and programmable interconnections. - W. Y. Lo; Chiu-sing Choy; Cheong-Fat Chan (RSP, 1994)

A Feedback Control Circuit Design Technique to Suppress Power Noise in High Speed Output Driver. - Chiu-sing Choy; Cheong-Fat Chan; M. H. Ku (ISCAS, 1995)

Test Generation with Dynamic Probe Points in High Observability Testing Environment. - Oliver Chiu-sing Choy; Lap-kong Chan; Ray Chan; Cheong-Fat Chan (IEEE Trans. Computers, 1996)

Incremental layout placement modification algorithms. - Chiu-sing Choy; Tsz-Shing Cheung; Kam-Keung Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Self-timed 1-D ICT processor. - Tin-Chak Johnson Pang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Wai-kuen Cham (ASP-DAC, 1997)

A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions. - Chiu-Sing Choy; M. H. Ku; Chi Fat Chan (IEEE J. Solid State Circuits, 1997)

A Useful Micropipeline Architecture to Implement DSP Algorithms. - Oliver Chiu-sing Choy; Tin-Chak Johnson Pang; Juraj Povazanec; Cheong-Fat Chan (EUROMICRO, 1998)

Asynchronous logic in bit-serial arithmetic. - Juraj Povazanec; Chiu-Sing Choy; Cheong-Fat Chan (ICECS, 1998)

Pipelined Dataflow Architecture of a Small Processor. - Juraj Povazanec; Oliver Chiu-sing Choy; Cheong-Fat Chan; Jan Butas; Yeu-qiu Zhang; Jing-Ling Yang; Tin-yan Tang (PDPTA, 1999)

A four-phase handshaking asynchronous static RAM design for self-timed systems. - Vincent Wing-Yun Sit; Chiu-Sing Choy; Cheong-Fat Chan (IEEE J. Solid State Circuits, 1999)

A self-timed ICT chip for image coding. - Tin-Chak Johnson Pang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Wai-kuen Cham (IEEE Trans. Circuits Syst. Video Technol., 1999)

Design of self-timed asynchronous Booth's multiplier. - Tin-Y. Tang; Chiu-sing Choy; Pui-Lam Siu; Cheong-Fat Chan (ASP-DAC, 2000)

An 8×8 adiabatic quasi-static CMOS multiplier. - Wing-Sum Mak; Cheong-Fat Chan; Ka-Wai Cheung; Chiu-Sing Choy (ISCAS, 2000)

An ALU design using a novel asynchronous pipeline architecture. - Tin-Yau Tang; Chiu-sing Choy; Jan Butas; Cheong-Fat Chan (ISCAS, 2000)

CMOS high speed interpolators based on parallel architecture. - Hongwei Wang; Cheong-Fat Chan; Chiu-sing Choy (IEEE Trans. Consumer Electron., 2000)

High speed CMOS digital-to-analog converter with linear interpolator. - Hongwei Wang; Cheong-Fat Chan; Chiu-sing Choy (IEEE Trans. Consumer Electron., 2000)

A pipelined dataflow small micro-coded asynchronous processor and its application to DCT. - Chi-Wai Lee; Chiu-sing Choy; Jan Butas; Cheong-Fat Chan (ISCAS (4), 2001)

A giga-hertz CMOS digital controlled oscillator. - Lai-Kan Leung; Cheong-Fat Chan; Oliver Chiu-sing Choy (ISCAS (4), 2001)

A low power asynchronous DES. - Pui-Lam Siu; Chiu-sing Choy; Jan Butas; Cheong-Fat Chan (ISCAS (4), 2001)

Asynchronous cross-pipelined multiplier. - Jan Butas; Chiu-Sing Choy; Juraj Povazanec; Cheong-Fat Chan (IEEE J. Solid State Circuits, 2001)

A self-timed divider using a new fast and robust pipeline scheme. - Jing-Ling Yang; Chiu-Sing Choy; Cheong-Fat Chan (IEEE J. Solid State Circuits, 2001)

A New Control Circuit for Asynchronous Micropipelines. - Oliver Chiu-sing Choy; Jan Butas; Juraj Povazanec; Cheong-Fat Chan (IEEE Trans. Computers, 2001)

A 900 MHz 1.2 V CMOS mixer with high linearity. - Wang-Chi Cheng; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (APCCAS (1), 2002)

A Totally Self-Checking Dynamic Asynchronous Datapath. - Jing-Ling Yang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (Asian Test Symposium, 2002)

A 1.2 V 900 MHz CMOS mixer. - Wang-Chi Cheng; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (ISCAS (5), 2002)

A CMOS current feedback operational amplifier with active current mode compensation. - Kin-Pui Ho; Cheong-Fat Chan; Chiu-sing Choy; Kong-Pang Pun (ISCAS (1), 2002)

A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators. - Kong-Pang Pun; Chiu-sing Choy; Cheong-Fat Chan; José E. Franca (ISCAS (4), 2002)

A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter. - Hongwei Wang; Cheong-Fat Chan; Chiu-sing Choy (ISCAS (3), 2002)

A contactless smartcard designed with asynchronous circuit technique. - Pui-Lam Siu; Chiu-Sing Choy; Chi Fat Chan; Kong-Pang Pun (ESSCIRC, 2003)

An HMM-based speech recognition IC. - Wei Han; Kwok-Wai Hon; Cheong-Fat Chan; Tan Lee 001; Chiu-sing Choy; Kong-Pang Pun; Pak-Chung Ching (ISCAS (2), 2003)

A low power asynchronous GF(2173) ALU for elliptic curve crypto-processor. - Pak-Keung Leung; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (ISCAS (5), 2003)

Clock recovery circuit with adiabatic technology (quasi-static CMOS logic). - W. K. Yeung; Cheong-Fat Chan; Chiu-sing Choy; Kong-Pang Pun (ISCAS (2), 2003)

Design for Self-Checking and Self-Timed Datapath. - Jing-Ling Yang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (VTS, 2003)

Reversed nested Miller compensation with voltage buffer and nulling resistor. - Kin-Pui Ho; Cheong-Fat Chan; Chiu-Sing Choy; Kong-Pang Pun (IEEE J. Solid State Circuits, 2003)

A low power asynchronous Java processor for contactless smart card. - Chun-Pong Yu; Chiu-sing Choy; Hao Min; Cheong-Fat Chan; Kong-Pang Pun (ASP-DAC, 2004)

Card-Centric Framework - Providing I/O Resources for Smart Cards. - Pak-Kee Chan; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (CARDIS, 2004)

An IF input continuous-time sigma-delta analog-digital converter with high image rejection. - Junhua Shen; Kong-Pang Pun; Chiu-sing Choy; Cheong-Fat Chan (ICECS, 2004)

An asynchronous SOVA decoder for wireless communication application. - Wing-Kin Chan; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (ISCAS (2), 2004)

An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing. - Wang Tung Cheng; Kong-Pang Pun; Cheong-Fat Chan; Chiu-sing Choy (ISCAS (1), 2004)

Pipelines in Dynamic Dual-Rail Circuits. - Jing-Ling Yang; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (PATMOS, 2004)

A high-efficiency strongly self-checking asynchronous datapath. - Jing-Ling Yang; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A low-latency asynchronous shift register. - Ragnarok Pak-Kee Chan; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator. - Kong-Pang Pun; Chiu-sing Choy; Cheong-Fat Chan; José Epifânio da Franca (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Preparing smartcard for the future: from passive to active. - Pak-Kee Chan; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (IEEE Trans. Consumer Electron., 2004)

High Speed Curve Interpolating D/A Converter. - Hongwei Wang; Cheong-Fat Chan; Chiu-sing Choy (J. VLSI Signal Process., 2004)

A 75dB image rejection IF-input quadrature sampling SC ΣΔ modulator. - Wang Tung Cheng; Kong-Pang Pun; Chiu-Sing Choy; Cheong-Fat Chan (ESSCIRC, 2005)

A speech recognizer with selectable model parameters. - Wei Han; Cheong-Fat Chan; Chiu-sing Choy; Kong-Pang Pun (ISCAS (6), 2005)

Realization of card-centric framework: a card-centric computer [smart cards]. - Chi-Leung San; Chiu-sing Choy; Pak-Kee Chan; Cheong-Fat Chan; Kong-Pang Pun (ISCAS (5), 2005)

Ramp voltage supply using adiabatic charging principle. - Pui-Tak So; Cheong-Fat Chan; Chiu-sing Choy; Kong-Pang Pun (ISCAS (3), 2005)

Active RC filter with reduced capacitance by current division technique. - Nang-Ching Yeung; Kong-Pang Pun; Oliver Chiu-sing Choy; Cheong-Fat Chan (ISCAS (4), 2005)

Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System. - Wang-Chi Cheng; Cheong-Fat Chan; Kong-Pang Pun; Oliver Chiu-sing Choy (APCCAS, 2006)

0.8 V GPS band CMOS VCO with 29% Tuning Range. - Wang-Chi Cheng; Cheong-Fat Chan; Kong-Pang Pun; Oliver Chiu-sing Choy (APCCAS, 2006)

Adiabatic Smart Card. - King-Keung Mok; Ka-Hung Tsang; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (APCCAS, 2006)

A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm. - Chi-Hong Chan; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (ISCAS, 2006)

An efficient MFCC extraction method in speech recognition. - Wei Han; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (ISCAS, 2006)

A 0.5V fully differential OTA with local common feedback. - Xiao-Yong He; Kong-Pang Pun; Oliver Chiu-sing Choy; Cheong-Fat Chan (ISCAS, 2006)

An optimal normal basis elliptic curve cryptoprocessor for inductive RFID application. - Pak-Keung Leung; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (ISCAS, 2006)

A fully differential low noise amplifier with real-time channel hopping for ultra-wideband wireless applications. - Siu-Kei Tang; Kong-Pang Pun; Oliver Chiu-sing Choy; Cheong-Fat Chan (ISCAS, 2006)

An ECG measurement IC using driven-right-leg circuit. - Alex K. Y. Wong; Kong-Pang Pun; Yuan-Ting Zhang; Oliver Chiu-sing Choy (ISCAS, 2006)

Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder. - Ke Xu 014; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (ISCAS, 2006)

A 75-dB image rejection IF-input quadrature-sampling SC ΣΔ Modulator. - Kong-Pang Pun; Wang Tung Cheng; Chiu-Sing Choy; Cheong-Fat Chan (IEEE J. Solid State Circuits, 2006)

Low-power H.264/AVC baseline decoder for portable applications. - Ke Xu 014; Chiu-sing Choy (ISLPED, 2007)

Priority-Based Heading One Detector in H.264/AVC Decoding. - Ke Xu 014; Oliver Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (EURASIP J. Embed. Syst., 2007)

Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing. - Ke Xu 014; Chiu-sing Choy; Cheong-Fat Chan; Kong-Pang Pun (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities. - Wei Han; Kwok-Wai Hon; Cheong-Fat Chan; Oliver Chiu-sing Choy; Kong-Pang Pun (J. VLSI Signal Process., 2007)

Enhanced channel selection using digital low-IF in Weaver receiver architecture. - Misteltein Pak-Kee Chan; Oliver Chiu-sing Choy; Kong-Pang Pun; Cheong-Fat Chan; Alex Ka Nang Leung (APCCAS, 2008)

Design of passive UHF RFID tag in 130nm CMOS technology. - Yang Hong; Chi Fat Chan; Jianping Guo; Yuen Sum Ng; Weiwei Shi 001; Lincoln Lai Kan Leung; Ka Nang Leung; Chiu-sing Choy; Kong-Pang Pun (APCCAS, 2008)

Low-Cost VC Allocator Design for Virtual Channel Wormhole Routers in Networks-on-Chip. - Min Zhang 012; Chiu-sing Choy (NOCS, 2008)

A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers. - Siu-Kei Tang; Kong-Pang Pun; Oliver Chiu-sing Choy; Cheong-Fat Chan; Ka Nang Leung (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC. - Ke Xu 014; Chiu-sing Choy (IEEE Trans. Circuits Syst. Video Technol., 2008)

A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding. - Ke Xu 014; Oliver Chiu-sing Choy (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A comparison of via-programmable gate array logic cell circuits. - Thomas C. P. Chau; Philip Heng Wai Leong; Sam M. H. Ho; Brian P. W. Chan; Steve C. L. Yuen; Kong-Pang Pun; Oliver C. S. Choy; Xinan Wang (FPGA, 2009)

A Low-power Signal Processing Front-end and Decoder for UHF Passive RFID Transponders. - Chi Fat Chan; Weiwei Shi 001; Kong-Pang Pun; Lincoln Lai Kan Leung; Ka Nang Leung; Oliver Chiu-sing Choy (ISCAS, 2009)

Robust and Low Complexity Packet Detector Design for MB-OFDM UWB. - Wen Fan; Oliver Chiu-sing Choy; Ka Nang Leung (ISCAS, 2009)

A Novel Mismatch Cancellation and I/Q Channel Multiplexing Scheme for Quadrature Bandpass DeltaSigma Modulators. - Bing Li; Cheong-Fat Chan; Kong-Pang Pun; Oliver Chiu-sing Choy (ISCAS, 2009)

Low-Power Bitstream-Residual Decoder for H.264/AVC Baseline Profile Decoding. - Ke Xu 014; Oliver Chiu-sing Choy (EURASIP J. Embed. Syst., 2009)

Low-Cost Allocator Implementations for Networks-on-Chip Routers. - Min Zhang 012; Oliver Chiu-sing Choy (VLSI Design, 2009)

Performance evaluation of OFDM de-modulator with various multiplier architectures for UWB system. - Pui-wai Chan; Chiu-sing Choy (APCCAS, 2010)

Rapid prototyping on a structured ASIC fabric. - Steve C. L. Yuen; Yanqing Ai; Brian P. W. Chan; Thomas C. P. Chau; Sam M. H. Ho; Oscar K. L. Lau; Kong-Pang Pun; Philip Heng Wai Leong; Oliver C. S. Choy (ASP-DAC, 2010)

Design of a single layer programmable Structured ASIC library. - Thomas C. P. Chau; David W. L. Wu; Yanqing Ai; Brian P. W. Chan; Sam M. H. Ho; Oscar K. L. Lau; Steve C. L. Yuen; Kong-Pang Pun; Oliver C. S. Choy; Philip Heng Wai Leong (DDECS, 2010)

Structured ASIC: Methodology and comparison. - Sam M. H. Ho; Steve C. L. Yuen; Hiu Ching Poon; Thomas C. P. Chau; Yanqing Ai; Philip Heng Wai Leong; Oliver C. S. Choy; Kong-Pang Pun (FPT, 2010)

A low-latency NoC router with lookahead bypass. - Ling Xin; Chiu-sing Choy (ISCAS, 2010)

RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology. - Ka Nang Leung; Chiu-sing Choy; Kong-Pang Pun; Lincoln Lai Kan Leung; Jianping Guo; Yuen Sum Ng; Chi Fat Chan; Weiwei Shi 001; Yang Hong; Marco Ho; Ki-Leung Mak; Yanqing Ai (J. Low Power Electron., 2010)

A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders. - Chi Fat Chan; Kong-Pang Pun; Ka Nang Leung; Jianping Guo; Lincoln Lai Kan Leung; Oliver Chiu-sing Choy (IEEE J. Solid State Circuits, 2010)

Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding. - Ke Xu 014; Tsu-Ming Liu; Jiun-In Guo; Oliver Chiu-sing Choy (J. Signal Process. Syst., 2010)

Robust and efficient baseband receiver design for MB-OFDM UWB system. - Wen Fan; Oliver Chiu-sing Choy (ASP-DAC, 2011)

A process-compatible passive RFID tag's digital design for subthreshold operation. - Weiwei Shi 001; Oliver Chiu-sing Choy (ICECS, 2012)

Robust, Low-Complexity, and Energy Efficient Downlink Baseband Receiver Design for MB-OFDM UWB System. - Wen Fan; Oliver Chiu-sing Choy (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Design a Low-Power H.264/AVC Baseline Decoder at All Abstraction Levels - A Showcase. - Ke Xu 014; Min Zhang 012; Chiu-sing Choy (J. Signal Process. Syst., 2012)

The Impact of Nodes Embedded with Data Processing Unit on Energy Consumption in a Wireless BAN. - Yanqing Ai; Oliver Chiu-sing Choy (ANT/SEIT, 2013)

Key component designs of subthreshold baseband processors in passive RF device. - Weiwei Shi 001; Oliver Chiu-sing Choy; Robert K. F. Teng (ASICON, 2013)

A data compression based power aware BAN system exploration of IEEE 802.15.6. - Yanqing Ai; Chiu-Sing Choy (ISCE, 2013)

Architecture and Design Flow for a Highly Efficient Structured ASIC. - S. Man Ho Ho; Yanqing Ai; Thomas Chun-Pong Chau; Steve C. L. Yuen; Oliver Chiu-sing Choy; Philip Heng Wai Leong; Kong-Pang Pun (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Simplifying HOG arithmetic for speedy hardware realization. - Jianfeng Wang; Chiu-sing Choy; Tak Lon Chao; Ko-Chun Kit; Kong-Pang Pun; Wanli Ouyang; Xiao-Gang Wang 001 (APCCAS, 2014)

Subthreshold passive RF tag's PIE decoder design with wide tolerance and custom ratioed logic cells. - Weiwei Shi 001; Oliver Chiu-sing Choy (ICECS, 2014)

Reducing pin count on cross-referencing Digital Microfluidic Biochip. - Ho Chuen Jackson Yeung; Evangeline F. Y. Young; Chiu-sing Choy (ISCAS, 2014)

A novel high speed, low power IntraBody Communication Receiver Front End based on sampling rate boosting switched-capacitor filter. - Hao Wang 030; Chiu-Sing Choy (MWSCAS, 2014)

A 2.5-Mbps, 170-cm transmission distance IntraBody communication receiver front end design and its synchronization technique research. - Hao Wang 030; Jianfeng Wang; Chiu-Sing Choy (MWSCAS, 2014)

A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below. - Weiwei Shi 001; Oliver Chiu-sing Choy (SoCC, 2014)

Subthreshold passive RFID tag's baseband processor core design with custom modules and cells. - Weiwei Shi 001; Linqing Fu; Chiu-sing Choy (ICECS, 2015)

A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s Advanced Techniques-Based Novel Intrabody Communication Receiver Analog Front End. - Hao Wang 030; Xian Tang; Chiu-sing Choy; Ka Nang Leung; Kong-Pang Pun (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Automatic seizure detection using correlation integral with nonlinear adaptive denoising and Kalman filter. - Hongda Wang; Chiu-sing Choy (EMBC, 2016)

Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells. - Weiwei Shi 001; Zhao Guangdong; Oliver Chiu-sing Choy (ISVLSI, 2016)

Deep sparse rectifier neural networks for speech denoising. - Lie Xu; Chiu-sing Choy; Yi-Wen Li (IWAENC, 2016)

A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption. - Weiwei Shi 001; Chiu-sing Choy (SoCC, 2016)

Cascaded Network Body Channel Model for Intrabody Communication. - Hao Wang 030; Xian Tang; Oliver Chiu-sing Choy; Gerald E. Sobelman (IEEE J. Biomed. Health Informatics, 2016)

Integrating channel selection and feature selection in a real time epileptic seizure detection system. - Hongda Wang; Weiwei Shi 001; Chiu-sing Choy (EMBC, 2017)

Spatial temporal GRU convnets for vision-based real time epileptic seizure detection. - Zhou Fang; Howan Leung; Chiu-sing Choy (ISBI, 2018)

Hardware Design of Real Time Epileptic Seizure Detection Based on STFT and SVM. - Hongda Wang; Weiwei Shi 001; Chiu-Sing Choy (IEEE Access, 2018)

A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags. - Weiwei Shi 001; An Pan; Shi Yu; Chiu-sing Choy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A 0.35 V 376 Mb/s Configurable Long Integer Multiplier for Subthreshold Encryption. - Weiwei Shi 001; Hai-Peng Wang; Chiu-Sing Choy; Junwei Yang; Mei Jiang; Robert K. F. Teng; Mingcheng Zhu 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Brillouin Optical Time Domain Analyzer Fiber Sensor Based on FPGA Accelerated Support Vector Regression. - Huan Wu; Hongda Wang; Chester Shu; Chiu-Sing Choy; Chao Lu 001 (OFC, 2019)

A 0.4 V 298 nJ/op Neural Signal Spectral Feature Extraction Module With Novel Approximate MACs and Custom Compressors. - Weiwei Shi 001; Yuan Xu; Chiu-Sing Choy; Zhiyong Chen; Junwei Yang; Robert K. F. Teng; Mei Jiang; X. Deng (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

BOTDA Fiber Sensor System Based on FPGA Accelerated Support Vector Regression. - Huan Wu; Hongda Wang; Chester Shu; Chiu-Sing Choy; Chao Lu 001 (IEEE Trans. Instrum. Meas., 2020)

A Platform for Adaptive Interference Mitigation and Intent Analysis Using OpenLANE. - Jinfa Hong; Hei Wong; Oliver C. S. Choy; Ray C. C. Cheung (ICSPCC, 2023)