Runtime adaptation on dataflow HPC platforms. - Riccardo Cattaneo; Christian Pilato; Matteo Mastinu; Oliver Kadlcek; Oliver Pell; Marco Domenico Santambrogio (AHS, 2013)

On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA's Configuration Infrastructure. - Karel Heyse; Dirk Stroobandt; Oliver Kadlcek; Oliver Pell (ARC, 2014)

On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip's Internal Configuration Infrastructure. - Karel Heyse; Jente Basteleus; Brahim Al Farisi; Dirk Stroobandt; Oliver Kadlcek; Oliver Pell (ACM Trans. Reconfigurable Technol. Syst., 2015)