Determining the minimal number of lines for large reversible circuits. - Robert Wille; Oliver Keszöcze; Rolf Drechsler (DATE, 2011)

Task-Driven Software Summarization. - Dave W. Binkley; Dawn J. Lawrie; Emily Hill 001; Janet E. Burge; Ian G. Harris; Regina Hebig; Oliver Keszöcze; Karl Reed; John Slankas (ICSM, 2013)

Exact One-pass Synthesis of Digital Microfluidic Biochips. - Oliver Keszöcze; Robert Wille; Tsung-Yi Ho; Rolf Drechsler (DAC, 2014)

Exact routing for digital microfluidic biochips with temporary blockages. - Oliver Keszöcze; Robert Wille; Rolf Drechsler (ICCAD, 2014)

A Logic for Cardinality Constraints (Extended Abstract). - Heinz Riener; Oliver Keszöcze; Rolf Drechsler; Görschwin Fey (MBMV, 2014)

Reverse BDD-based synthesis for splitter-free optical circuits. - Robert Wille; Oliver Keszöcze; Clemens Hopfmuller; Rolf Drechsler (ASP-DAC, 2015)

A General and Exact Routing Methodology for Digital Microfluidic Biochips. - Oliver Keszöcze; Robert Wille; Krishnendu Chakrabarty; Rolf Drechsler (ICCAD, 2015)

Scalable One-Pass Synthesis for Digital Microfluidic Biochips. - Robert Wille; Oliver Keszöcze; Rolf Drechsler; Tobias Boehnisch; Alexander Kroker (IEEE Des. Test, 2015)

Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits. - Robert Wille; Oliver Keszöcze; Marcel Walter; Patrick Rohrs; Anupam Chattopadhyay; Rolf Drechsler (ASP-DAC, 2016)

Synthesis of approximate coders for on-chip interconnects using reversible logic. - Robert Wille; Oliver Keszöcze; Stefan Hillmich; Marcel Walter; Alberto García Ortiz (DATE, 2016)

Generating and checking control logic in the HDL-based design of reversible circuits. - Robert Wille; Oliver Keszöcze; Lars Othmer; Michael Kirkedal Thomsen; Rolf Drechsler (ISED, 2016)

Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report. - Robert Wille; Oliver Keszöcze; Lars Othmer; Michael Kirkedal Thomsen; Rolf Drechsler (RC, 2016)

Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits. - Arighna Deb; Robert Wille; Oliver Keszöcze; Stefan Hillmich; Rolf Drechsler (ACM J. Emerg. Technol. Comput. Syst., 2016)

Embedding of Large Boolean Functions for Reversible Logic. - Mathias Soeken; Robert Wille; Oliver Keszöcze; D. Michael Miller; Rolf Drechsler (ACM J. Emerg. Technol. Comput. Syst., 2016)

Exact routing for micro-electrode-dot-array digital microfluidic biochips. - Oliver Keszöcze; Zipeng Li; Andreas Grimmer; Robert Wille; Krishnendu Chakrabarty; Rolf Drechsler (ASP-DAC, 2017)

Effects of cell shapes on the routability of Digital Microfluidic Biochips. - Leonard Schneider; Oliver Keszöcze; Jannis Stoppe; Rolf Drechsler (DATE, 2017)

Exakter Entwurf digitaler mikrofluidischer Biochips. - Oliver Keszöcze (Ausgezeichnete Informatikdissertationen, 2017)

BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips. - Jannis Stoppe; Oliver Keszöcze; Maximilian Luenert; Robert Wille; Rolf Drechsler (ISVLSI, 2017)

Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips. - Leonard Schneider; Oliver Keszöcze; Jannis Stoppe; Rolf Drechsler (MBMV, 2017)

Synthesis of optical circuits using binary decision diagrams. - Arighna Deb; Robert Wille; Oliver Keszöcze; Saeideh Shirinzadeh; Rolf Drechsler (Integr., 2017)

An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs. - Robert Wille; Oliver Keszöcze; Lars Othmer; Michael Kirkedal Thomsen; Rolf Drechsler (J. Low Power Electron., 2017)

Exact design of digital microfluidic biochips. - Oliver Keszöcze (2017)

Translating Between the Roots of the Identity in Quantum Computers. - Wouter Castryck; Jeroen Demeyer; Alexis De Vos; Oliver Keszöcze; Mathias Soeken (ISMVL, 2018)

Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws. - Kenneth Schmitz; Oliver Keszöcze; Jurij Schmidt; Daniel Große; Rolf Drechsler (ISVLSI, 2018)

Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips. - Oliver Keszöcze; Mohamed Ibrahim 002; Robert Wille; Krishnendu Chakrabarty; Rolf Drechsler (VLSID, 2018)

The complexity of error metrics. - Oliver Keszöcze; Mathias Soeken; Rolf Drechsler (Inf. Process. Lett., 2018)

On the complexity of design tasks for Digital Microfluidic Biochips. - Oliver Keszöcze; Philipp Niemann 001; Arved Friedemann; Rolf Drechsler (Microelectron. J., 2018)

Chatbot-based assertion generation from natural language specifications. - Oliver Keszöcze; Ian G. Harris (FDL, 2019)

Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. - Jürgen Teich; Behnaz Pourmohseni; Oliver Keszöcze; Jan Spieck; Stefan Wildermann (ASP-DAC, 2020)

Probabilistic Error Propagation through Approximated Boolean Networks. - Jorge Echavarria; Stefan Wildermann; Oliver Keszöcze; Jürgen Teich (DAC, 2020)

A fast BDD Minimization Framework for Approximate Computing. - Andreas Wendler; Oliver Keszöcze (DATE, 2020)

Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout. - Martin Lukac; Saadat Nursultan; Georgiy Krylov; Oliver Keszöcze (DSD, 2020)

One-pass Synthesis for Digital Microfluidic Biochips: A Survey. - Oliver Keszöcze; Robert Wille; Rolf Drechsler (ISDCS, 2020)

Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures. - Oliver Keszöcze; Naser Mohammadzadeh; Robert Wille (DATE, 2021)

Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs Using Accuracy-Programmable Instruction Set Processors. - Armin Schuster; Christian Heidorn; Marcel Brand; Oliver Keszöcze; Jürgen Teich (PKDD/ECML Workshops (1), 2021)

Aarith: an arbitrary precision number library. - Oliver Keszöcze; Marcel Brand; Michael Witterauf; Christian Heidorn; Jürgen Teich (SAC, 2021)

On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. - Jorge Echavarria; Stefan Wildermann; Oliver Keszöcze; Faramarz Khosravi; Andreas Becher; Jürgen Teich (CoRR, 2021)

Efficient One-pass Synthesis for Digital Microfluidic Biochips. - Naser Mohammadzadeh; Robert Wille; Oliver Keszöcze (ACM Trans. Design Autom. Electr. Syst., 2021)

DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. - Jan Sommer; M. Akif Özkan; Oliver Keszöcze; Jürgen Teich (FPL, 2022)

Using Deep Learning to Demodulate Transmissions in Molecular Communication. - Max Bartunik; Oliver Keszöcze; Benjamin Schiller; Jens Kirchner (ISMICT, 2022)

BDD-Based Error Metric Analysis, Computation and Optimization. - Oliver Keszöcze (IEEE Access, 2022)

Towards Clause Learning à la Carte through VarMonads. - Arved Friedemann; Oliver Keszöcze (CoRR, 2022)

Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. - Jorge Echavarria; Stefan Wildermann; Oliver Keszöcze; Faramarz Khosravi; Andreas Becher; Jürgen Teich (it Inf. Technol., 2022)

Approximate Computing. - Oliver Keszöcze (it Inf. Technol., 2022)

Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. - Jan Sommer; M. Akif Özkan; Oliver Keszöcze; Jürgen Teich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. - Marcel Brand; Frank Hannig; Oliver Keszöcze; Jürgen Teich (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. - Patrick Plagwitz; Frank Hannig; Jürgen Teich; Oliver Keszöcze (CoRR, 2023)

Artificial intelligence for molecular communication. - Max Bartunik; Jens Kirchner; Oliver Keszöcze (it Inf. Technol., 2023)

SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. - Patrick Plagwitz; Frank Hannig; Jürgen Teich; Oliver Keszöcze (ARC, 2024)

SAS - A Framework for Symmetry-based Approximate Synthesis. - Niklas Jungnitz; Oliver Keszöcze (DAC, 2024)

DSL-Based SNN Accelerator Design Using Chisel. - Patrick Plagwitz; Frank Hannig; Jürgen Teich; Oliver Keszöcze (DSD, 2024)

Hardware Generators with Chisel. - Martin Schoeberl; Hans Jakob Damsgaard; Luca Pezzarossa; Oliver Keszöcze; Erling Rennemo Jellum (DSD, 2024)

Markov Chain-based Optimization Time Analysis of Bivalent Ant Colony Optimization for Sorting and LeadingOnes. - Matthias Kergaßner; Oliver Keszöcze; Rolf Wanka (GECCO, 2024)

Geometric Refactoring of Quantum and Reversible Circuits Using Graph Algorithms. - Martin Lukac; Saadat Nursultan; Georgiy Krylov; Oliver Keszöcze; Abilmansur Rakhmettulayev; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2024)

Approximate synthesis for LUT count reduction via probabilistic error propagation. - Thomas Schlögl; Oliver Keszöcze (it Inf. Technol., 2024)

Binarization and Classification of RGB Images. - Tagir Nukenov; Kamila Abdiyeva; Oliver Keszöcze; Shinobu Nagayama; Martin Lukac (ISMVL, 2025)