Correlation-Enhanced Power Analysis Collision Attack. - Amir Moradi 001; Oliver Mischke; Thomas Eisenbarth 001 (IACR Cryptol. ePrint Arch., 2010)

On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting. - Amir Moradi 001; Oliver Mischke; Christof Paar; Yang Li 001; Kazuo Ohta; Kazuo Sakiyama (CHES, 2011)

Practical evaluation of DPA countermeasures on reconfigurable hardware. - Amir Moradi 001; Oliver Mischke; Christof Paar (HOST, 2011)

MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processor. - Michal Varchola; Tim Güneysu; Oliver Mischke (ReConFig, 2011)

Collision Timing Attack when Breaking 42 AES ASIC Cores. - Amir Moradi 001; Oliver Mischke; Christof Paar (IACR Cryptol. ePrint Arch., 2011)

How Far Should Theory Be from Practice? - Evaluation of a Countermeasure. - Amir Moradi 001; Oliver Mischke (CHES, 2012)

Glitch-free implementation of masking in modern FPGAs. - Amir Moradi 001; Oliver Mischke (HOST, 2012)

IPSecco: A lightweight and reconfigurable IPSec core. - Benedikt Driessen; Tim Güneysu; Elif Bilge Kavun; Oliver Mischke; Christof Paar; Thomas Pöppelmann (ReConFig, 2012)

On the Simplicity of Converting Leakages from Multivariate to Univariate - Case Study of a Glitch-Resistant Masking Scheme - - Amir Moradi 001; Oliver Mischke (IACR Cryptol. ePrint Arch., 2012)

Side channels as building blocks. - Markus Kasper; Amir Moradi 001; Georg T. Becker; Oliver Mischke; Tim Güneysu; Christof Paar; Wayne P. Burleson (J. Cryptogr. Eng., 2012)

Comprehensive Evaluation of AES Dual Ciphers as a Side-Channel Countermeasure. - Amir Moradi 001; Oliver Mischke (ICICS, 2013)

One Attack to Rule Them All: Collision Timing Attack versus 42 AES ASIC Cores. - Amir Moradi 001; Oliver Mischke; Christof Paar (IEEE Trans. Computers, 2013)

MicroACP - A Fast and Secure Reconfigurable Asymmetric Crypto-Processor - -Overhead Evaluation of Side-Channel Countermeasures-. - Christopher Pöpper; Oliver Mischke; Tim Güneysu (ARC, 2014)

Fault Sensitivity Analysis Meets Zero-Value Attack. - Oliver Mischke; Amir Moradi 001; Tim Güneysu (FDTC, 2014)

Side-Channel Protection by Randomizing Look-Up Tables on Reconfigurable Hardware - Pitfalls of Memory Primitives. - Pascal Sasdrich; Oliver Mischke; Amir Moradi 001; Tim Güneysu (IACR Cryptol. ePrint Arch., 2015)

Achieving Side-Channel Protection with Dynamic Logic Reconfiguration on Modern FPGAs. - Pascal Sasdrich; Amir Moradi 001; Oliver Mischke; Tim Güneysu (IACR Cryptol. ePrint Arch., 2015)

Physical attacks and countermeasures on the advanced encryption standard. - Oliver Mischke (2016)

Cache attacks and countermeasures for NTRUEncrypt on MPSoCs: Post-quantum resistance for the IoT. - Johanna Sepúlveda; Andreas Zankl; Oliver Mischke (SoCC, 2017)

Practical Evaluation of Masking for NTRUEncrypt on ARM Cortex-M4. - Thomas Schamberger; Oliver Mischke; Johanna Sepúlveda (COSADE, 2019)