A power-constrained design strategy for CMOS tuned low noise amplifiers. - Oliver Mitea; Manfred Glesner (Microelectron. Reliab., 2004)

Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. - Tudor Murgan; Oliver Mitea; Sujan Pandey; Petru Bogdan Bacinschi; Manfred Glesner (VLSI-SoC, 2006)

Automated constraint-driven topology synthesis for analog circuits. - Oliver Mitea; Markus Meissner; Lars Hedrich; P. Jores (DATE, 2011)

Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts. - Oliver Mitea; Markus Meissner; Lars Hedrich (VLSI-SoC, 2011)

Fast isomorphism testing for a graph-based analog circuit synthesis framework. - Markus Meissner; Oliver Mitea; Linda Luy; Lars Hedrich (DATE, 2012)