A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. - Andreas Hoffmann 002; Oliver Schliebusch; Achim Nohl; Gunnar Braun; Oliver Wahlen; Heinrich Meyr (ICCAD, 2001)

A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. - Andreas Hoffmann 002; Tim Kogel; Achim Nohl; Gunnar Braun; Oliver Schliebusch; Oliver Wahlen; Andreas Wieferink; Heinrich Meyr (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Architecture Implementation Using the Machine Description Language LISA. - Oliver Schliebusch; Andreas Hoffmann 002; Achim Nohl; Gunnar Braun; Heinrich Meyr (ASP-DAC/VLSI Design, 2002)

Instruction encoding synthesis for architecture exploration using hierarchical processor models. - Achim Nohl; Volker Greive; Gunnar Braun; Andreas Hoffmann 002; Rainer Leupers; Oliver Schliebusch; Heinrich Meyr (DAC, 2003)

Processor/Memory Co-Exploration on Multiple Abstraction Levels. - Gunnar Braun; Andreas Wieferink; Oliver Schliebusch; Rainer Leupers; Heinrich Meyr; Achim Nohl (DATE, 2003)

RTL Processor Synthesis for Architecture Exploration and Implementation. - Oliver Schliebusch; Anupam Chattopadhyay; Rainer Leupers; Gerd Ascheid; Heinrich Meyr; Mario Steinert; Gunnar Braun; Achim Nohl (DATE, 2004)

A universal technique for fast and flexible instruction-set architecture simulation. - Gunnar Braun; Achim Nohl; Andreas Hoffmann 002; Oliver Schliebusch; Rainer Leupers; Heinrich Meyr (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. - Oliver Schliebusch; Anupam Chattopadhyay; David Kammler; Gerd Ascheid; Rainer Leupers; Heinrich Meyr; Tim Kogel (ASP-DAC, 2005)

Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation. - Ernst Martin Witte; Anupam Chattopadhyay; Oliver Schliebusch; David Kammler (ICCD, 2005)

Optimization Techniques for ADL-Driven RTL Processor Synthesis. - Oliver Schliebusch; Anupam Chattopadhyay; Ernst Martin Witte; David Kammler; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (IEEE International Workshop on Rapid System Prototyping, 2005)

Automatic ADL-based operand isolation for embedded processors. - Anupam Chattopadhyay; Benedikt Geukes; David Kammler; Ernst Martin Witte; Oliver Schliebusch; Harold Ishebabi; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (DATE, 2006)

ASIP design and synthesis for non linear filtering in image processing. - Luca Fanucci; Michele Cassiano; Sergio Saponara; David Kammler; Ernst Martin Witte; Oliver Schliebusch; Gerd Ascheid; Rainer Leupers; Heinrich Meyr (DATE Designers' Forum, 2006)

Optimized ASIP synthesis from architecture description language models. - Oliver Schliebusch; Heinrich Meyr; Rainer Leupers (Kluwer, 2007)