HDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken. - Frank Winkler 001; Gerald Kell; Oliver Schrape; Hans Gustat; Ulrich Jagdhold (MBMV, 2009)

An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis. - Oliver Schrape; Frank Winkler 001; Steffen Zeidler 001; Markus Petri; Eckhard Grass; Ulrich Jagdhold (PATMOS, 2010)

Sensor node processor for security applications. - Goran Panic; Thomas Basmer; Oliver Schrape; Steffen Peter; Frank Vater; Klaus Tittelbach-Helmrich (ICECS, 2011)

Embedded low power clock generator for sensor nodes. - Oliver Schrape; Frank Vater (NORCHIP, 2012)

GALS Design for Spectral Peak Attenuation of Switching Current. - Xin Fan 003; Oliver Schrape; Miroslav Marinkovic; Peter Dahnert; Milos Krstic; Eckhard Grass (ASYNC, 2013)

A 12 Gb/s standard cell based ECL 4: 1 serializer with asynchronous parallel interface. - Oliver Schrape; Markus Appel; Frank Winkler 001; Milos Krstic (ICECS, 2013)

TNODE: A low power sensor node processor for secure wireless networks. - Goran Panic; Oliver Schrape; Thomas Basmer; Frank Vater; Klaus Tittelbach-Helmrich (ISSoC, 2013)

Low-power design methodology for CML and ECL circuits. - Oliver Schrape; Markus Appel; Frank Winkler 001; Milos Krstic (PATMOS, 2014)

A Design Preconditioning Flow for Low-Noise Circuits. - Steffen Zeidler 001; Xin Fan 003; Oliver Schrape; Milos Krstic (DDECS, 2015)

Implementation of DBFN processor for Synthetic Aperture Radar application. - Oliver Schrape; Arkadiusz Koczor; Piotr Penkala; Vladimir Petrovic; Milos Krstic (DDECS, 2016)

An Early Stage Design Flow for Switching Noise Attenuation. - Steffen Zeidler 001; Xin Fan 003; Oliver Schrape; Milos Krstic (J. Circuits Syst. Comput., 2016)

Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling. - Xin Fan 003; Mikkel B. Stegmann; Oliver Schrape; Steffen Zeidler 001; Isac G. Jensen; Jannich Thorsen; Tobias Bjerregaard; Milos Krstic (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins. - Oliver Schrape; Manuel Herrmann; Frank Winkler 001; Milos Krstic (DDECS, 2017)

A single chip 16 GS/s arbitrary waveform generator in 0.13 μm BiCMOS technology. - P. Ostrovsky; Klaus Tittelbach-Helmrich; Frank Herzel; Oliver Schrape; Gunter Fischer; Dietmar Kissinger; P. Borner; A. Loose; D. Hellmann; P. Hartogh (NORCAS, 2017)

Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip. - Mahdi Tala; Oliver Schrape; Milos Krstic; Davide Bertozzi (DCIS, 2018)

Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle. - Yuanqing Li; Anselm Breitenreiter; Marko S. Andjelkovic; Oliver Schrape; Milos Krstic (DDECS, 2018)

D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop. - Oliver Schrape; Anselm Breitenreiter; Marko S. Andjelkovic; Milos Krstic (DSD, 2018)

Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment. - Mahdi Tala; Oliver Schrape; Milos Krstic; Davide Bertozzi (ACM Great Lakes Symposium on VLSI, 2018)

Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates. - Marko S. Andjelkovic; Milan Babic; Yuanqing Li; Oliver Schrape; Milos Krstic; Rolf Kraemer (ICECS, 2018)

A Radiation Hardened 16 GS/s Arbitrary Waveform Generator IC for a Submillimeter Wave Chirp-Transform Spectrometer. - P. Ostrovsky; Oliver Schrape; Klaus Tittelbach-Helmrich; Frank Herzel; Gunter Fischer; D. Hellmann; P. Borner; A. Loose; P. Hartogh; Dietmar Kissinger (NORCAS, 2018)

Master-Clone Placement with Individual Clock Tree Implementation - a Case on Physical Chip Design. - Oliver Schrape; Alexey Balashov; Aleksandar Simevski; Carlos Benito; Milos Krstic (NORCAS, 2018)

Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops. - Oliver Schrape; Anselm Breitenreiter; Steffen Zeidler 001; Milos Krstic (DSD, 2019)

Selective Fault Tolerance by Counting Gates with Controlling Value. - Anselm Breitenreiter; Stefan Weidling; Oliver Schrape; Steffen Zeidler 001; Pedro Reviriego; Milos Krstic (IOLTS, 2019)

Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures. - Felipe A. Kuentzer; Moisés Herrera; Oliver Schrape; Peter A. Beerel; Milos Krstic (ASYNC, 2020)

A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks. - Steffen Zeidler 001; Oliver Schrape; Anselm Breitenreiter; Milos Krstic (DSD, 2020)

Design of Radiation Hardened RADFET Readout System for Space Applications. - Marko S. Andjelkovic; Aleksandar Simevski; Junchao Chen 001; Oliver Schrape; Zoran Stamenkovic; Milos Krstic; Stefan D. Ilic; Luka Spahic; Laza Kostic; Goran S. Ristic; Aleksandar Jaksic; Alberto J. Palma; et al. (DSD, 2020)

Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops. - Oliver Schrape; Marko S. Andjelkovic; Anselm Breitenreiter; Alexey Balashov; Milos Krstic (DSD, 2020)

Characterization of Single Event Transient Effects in Standard Delay Cells. - Marko S. Andjelkovic; Oliver Schrape; Anselm Breitenreiter; Milos Krstic; Rolf Kraemer (ICECS, 2020)

PISA: Power-robust Multiprocessor Design for Space Applications. - Aleksandar Simevski; Oliver Schrape; Carlos Benito; Milos Krstic; Marko S. Andjelkovic (IOLTS, 2020)

R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints. - Christos Georgakidis; Christos P. Sotiriou; Nikolaos Sketopoulos; Milos Krstic; Oliver Schrape; Anselm Breitenreiter (ISVLSI, 2020)

A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay Cells. - Marko S. Andjelkovic; Oliver Schrape; Anselm Breitenreiter; Junchao Chen 001; Milos Krstic (DFT, 2021)

Power- and Area-optimized Neural Network IC-Design for Academic Education. - Florian Frankreiter; Anselm Breitenreiter; Oliver Schrape; Milos Krstic (ICECS, 2021)

Reliability Analysis in Less than 200 Lines of Code. - Anselm Breitenreiter; Oliver Schrape; Marko S. Andjelkovic; Milos Krstic (LASCAS, 2021)

Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops. - Oliver Schrape; Anselm Breitenreiter; Carsten Schulze; Steffen Zeidler 001; Milos Krstic (LASCAS, 2021)

Machine Learning Approach for Accelerating Simulation-based Fault Injection. - Li Lu; Junchao Chen 001; Anselm Breitenreiter; Oliver Schrape; Markus Ulbricht 002; Milos Krstic (NorCAS, 2021)

Monitoring of Particle Flux and LET Variations with Pulse Stretching Inverters. - Marko S. Andjelkovic; Junchao Chen 001; Aleksandar Simevski; Oliver Schrape; Milos Krstic; Rolf Kraemer (CoRR, 2021)

Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops. - Oliver Schrape; Marko S. Andjelkovic; Anselm Breitenreiter; Steffen Zeidler 001; Alexey Balashov; Milos Krstic (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Ultra High-Speed BP Decoder for Polar Codes achieving 1.4 Tbps in 28 nm CMOS. - Lukasz Lopacinski; Alireza Hasani; Goran Panic; Nebojsa Maletic; Oliver Schrape; Jesús Gutiérrez 004; Milos Krstic; Eckhard Grass (EuCNC, 2022)

Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS. - Lukasz Lopacinski; Alireza Hasani; Goran Panic; Nebojsa Maletic; Oliver Schrape; Jesús Gutiérrez 004; Milos Krstic; Eckhard Grass; Rolf Kraemer (VTC Spring, 2022)

Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting. - Anselm Breitenreiter; Marko S. Andjelkovic; Oliver Schrape; Milos Krstic (IEEE Access, 2022)

A design concept for radiation hardened RADFET readout system for space applications. - Marko S. Andjelkovic; Aleksandar Simevski; Junchao Chen 001; Oliver Schrape; Zoran Stamenkovic; Milos Krstic; Stefan D. Ilic; Goran S. Ristic; Aleksandar Jaksic; Nikola Vasovic; Russell Duane; Alberto J. Palma; et al. (Microprocess. Microsystems, 2022)

Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors. - Marko S. Andjelkovic; Milos Marjanovic; Bojan Drasko; Cristiano Calligaro; Oliver Schrape; Umberto Gatti; Felipe A. Kuentzer; Stefan D. Ilic; Goran S. Ristic; Milos Krstic (J. Circuits Syst. Comput., 2022)

SET and SEU Hardened Clock Gating Cell. - Marko S. Andjelkovic; Oliver Schrape; Anselm Breitenreiter; Milos Krstic (DCIS, 2023)

Methodology for standard cell-based design and implementation of reliable and robust hardware systems (Methoden für Standardzellbasiertes Design und Implementierung zuverlässiger und robuster Hardware Systeme) - Oliver Schrape (2023)

Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction. - Oliver Schrape; Anselm Breitenreiter; Li Lu; Marko S. Andjelkovic; Ernesto Pun-Garcia; Marisa López-Vallejo; Milos Krstic (NorCAS, 2024)

ImSTDP: Implicit Timing On-Chip STDP Learning. - Dedong Zhao; Oliver Schrape; Zoran Stamenkovic; Milos Krstic (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)