A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays. - Michael Gansen; Frank Richter; Oliver Weiss; Tobias G. Noll (ASAP, 1997)

A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. - V. S. Gierenz; Oliver Weiss; Tobias G. Noll; I. Carew; Jonathan J. Ashley; Razmik Karabed (ASAP, 2000)

Semi Custom Design: A Case Study on SIMD Shufflers. - Praveen Raghavan; Nandhavel Sethubalasubramanian; Satyakiran Munaga; Estela Rey Ramos; Murali Jayapala; Oliver Weiss; Francky Catthoor; Diederik Verkest (PATMOS, 2007)

An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS. - Ramin Farjadrad; Kambiz Kaviani; David Nguyen; Michael Brown; Govert Geelen; Corné Bastiaansen; Narendra Rao; Viswa Popuri; Greg Shen; Hamid Khatibi; Saudas Dey; Anirban Chatterjee; et al. (ISSCC, 2021)