Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. - Matthias Beck; Olivier Barondeau; Martin Kaibel; Frank Poehl; Xijiang Lin; Ron Press (DATE, 2005)

Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. - Matthias Beck; Olivier Barondeau; Frank Poehl; Xijiang Lin; Ron Press (VTS, 2005)

Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment. - Frank-Uwe Faber; Matthias Beck; Markus Rudack; Olivier Barondeau; Thomas Rabenalt; Michael Gössel; Andreas Leininger (ETS, 2009)