Instruction Based BIST for Board/System Level Test of External Memories and Internconnects. - Olivier Caty; Ismet Bayraktaroglu; Amitava Majumdar 002; Richard Lee; John Bell; Lisa Curhan (ITC, 2003)

Microprocessor silicon debug based on failure propagation tracing. - Olivier Caty; Peter Dahlgren; Ismet Bayraktaroglu (ITC, 2005)

Highly Configurable Programmable Built-In Self Test Architecture for High-Speed Memories. - Ismet Bayraktaroglu; Olivier Caty; Yickkei Wong (VTS, 2005)

Transition Test on UltraSPARC- T2 Microprocessor. - Liang-Chi Chen; Paul Dickinson; Prasad Mantri; Murali M. R. Gala; Peter Dahlgren; Subhra Bhattacharya; Olivier Caty; Kevin Woodling; Thomas A. Ziaja; David Curwen; Wendy Yee; Ellen Su; et al. (ITC, 2008)

Using transition test to understand timing behavior of logic circuits on UltraSPARCTM T2 family. - Liang-Chi Chen; Paul Dickinson; Peter Dahlgren; Scott Davidson 001; Olivier Caty; Kevin Wu (ITC, 2009)

A Phase Field Approach to Limited-angle Tomographic Reconstruction. - Léonard Turpin; Stéphane Roux; Olivier Caty; Sébastien Denneulin (Fundam. Informaticae, 2020)