Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below. - Claire Fenouillet-Béranger; P. Perreau; S. Denorme; L. Tosti; François Andrieu; Olivier Weber; S. Barnola; C. Arvet; Y. Campidelli; Sébastien Haendler; R. Beneyton; C. Perrot; et al. (ESSCIRC, 2009)

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits. - Shashikanth Bobba; Ashutosh Chakraborty; Olivier Thomas; Perrine Batude; Thomas Ernst 005; Olivier Faynot; David Z. Pan; Giovanni De Micheli (ASP-DAC, 2011)

3D monolithic integration. - Perrine Batude; Maud Vinet; Arnaud Pouydebasque; Cyrille Le Royer; Bernard Previtali; Claude Tabone; Jean-Michel Hartmann; Loic Sanchez; Laurence Baud; Veronique Carron; Alain Toffoli; Fabienne Allain; et al. (ISCAS, 2011)

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities. - Veeresh Deshpande; Sylvain Barraud; Xavier Jehl; Romain Wacquez; Maud Vinet; Remi Coquand; B. Roche; B. Voisin; François Triozon; C. Vizioz; L. Tosti; Bernard Previtali; et al. (ESSDERC, 2012)

Multibranch mobility characterization: Evidence of carrier mobility enhancement by back-gate biasing in FD-SOI MOSFET. - Carlos Navarro; Noel Rodriguez; Luca Donetti; Akiko Oliata; Francisco Gámiz; François Andrieu; Olivier Faynot; Claire Fenouillet-Béranger; Sorin Cristoloveanu (ESSDERC, 2012)

Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below. - J. Mazurier; Olivier Weber; François Andrieu; Alain Toffoli; Olivier Thomas; Fabienne Allain; Jean-Philippe Noel; Marc Belleville; Olivier Faynot; T. Poiroux (J. Low Power Electron., 2012)

Deep-amorphization and solid-phase epitaxial regrowth processes for hybrid orientation technologies in SOI MOSFETs with thin body. - Akiko Ohata; Young-Ho Bae; Sorin Cristoloveanu; Thomas Signamarcheix; J. Widiez; Bruno Ghyselen; Olivier Faynot; Laurent Clavelier (Microelectron. Reliab., 2012)

Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations. - Remi Coquand; Sylvain Barraud; Mikaël Cassé; Masahiro Koyama; Virginie Maffini-Alvaro; Marie-Pierre Samson; Lucie Tosti; Xavier Mescot; Gérard Ghibaudo; Stéphane Monfray; Frédéric Boeuf; Olivier Faynot; et al. (ESSDERC, 2013)

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. - François Andrieu; Mikaël Cassé; E. Baylac; P. Perreau; O. Nier; Denis Rideau; R. Berthelon; Franck Pourchon; A. Pofelski; Barbara De Salvo; C. Gallon; Vincent Mazzocchi; et al. (ESSDERC, 2014)

Variability of planar Ultra-Thin Body and Buried oxide (UTBB) FDSOI MOSFETs. - J. Mazurier; Olivier Weber; François Andrieu; Cyrille Le Royer; Olivier Faynot; Maud Vinet (ICICDT, 2014)

A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool. - Olivier Billoint; Hossam Sarhan; Iyad Rayane; Maud Vinet; Perrine Batude; Claire Fenouillet-Béranger; Olivier Rozeau; Gerald Cibrario; Fabien Deprat; A. Fustier; Julien Michallet; Olivier Faynot; et al. (DATE, 2015)

Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model. - J. Pelloux-Prayer; Mikaël Cassé; François Triozon; Sylvain Barraud; Yann-Michel Niquet; J.-L. Rouviere; Olivier Faynot; Gilles Reimbold (ESSDERC, 2015)

Performance and reliability of strained SOI transistors for advanced planar FDSOI technology. - Guillaume Besnard; Xavier Garros; Alexandre Subirats; François Andrieu; X. Federspiel; M. Rafik; Walter Schwarzenbach; Gilles Reimbold; Olivier Faynot; Sorin Cristoloveanu (IRPS, 2015)

Analog performance of strained SOI nanowires down to 10K. - Bruna Cardoso Paz; Marcelo Antonio Pavanello; Mikaël Cassé; Sylvain Barraud; Gilles Reimbold; Maud Vinet; Olivier Faynot (ESSDERC, 2016)

Opportunities brought by sequential 3D CoolCube™ integration. - Maud Vinet; Perrine Batude; Claire Fenouillet-Béranger; Laurent Brunet; Vincent Mazzocchi; Cao-Minh Vincent Lu; Fabien Deprat; Jessy Micout; Bernard Previtali; Paul Besombes; Nils Rambal; François Andrieu; et al. (ESSDERC, 2016)

Drain current model for short-channel triple gate junctionless nanowire transistors. - Bruna Cardoso Paz; Mikaël Cassé; Sylvain Barraud; Gilles Reimbold; Olivier Faynot; F. Avila-Herrera; Antonio Cerdeira; Marcelo Antonio Pavanello (Microelectron. Reliab., 2016)

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K. - Bruna Cardoso Paz; Renan Trevisoli Doria; Mikaël Cassé; Sylvain Barraud; Gilles Reimbold; Maud Vinet; Olivier Faynot; Marcelo Antonio Pavanello (Microelectron. Reliab., 2017)

Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs. - Yiming Qu; Ran Cheng; Wei Liu; Junkang Li; Bich-Yen Nguyen; Olivier Faynot; Nuo Xu; Bing Chen; Yi Zhao 015 (IRPS, 2018)

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors. - Michelly de Souza; Sylvain Barraud; Mikaël Cassé; Maud Vinet; Olivier Faynot; Marcelo Antonio Pavanello (ESSDERC, 2021)

Experimental Decomposition of the Carrier Mobility in the Conduction Planes of 2-Level Stacked Nanowires. - Giovanni Almeida Matos; Jaime CalÇade Rodrigues; Michelly de Souza; Mikaël Cassé; Sylvain Barraud; Olivier Faynot; Marcelo Antonio Pavanello (CCE, 2024)