ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. - Olivier Muller; Amer Baghdadi; Michel Jézéquel (DATE, 2006)

On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. - Olivier Muller; Amer Baghdadi; Michel Jézéquel (GLOBECOM, 2006)

Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. - Hazem Moussa; Olivier Muller; Amer Baghdadi; Michel Jézéquel (DATE, 2007)

From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. - Olivier Muller; Amer Baghdadi; Michel Jézéquel (IEEE International Workshop on Rapid System Prototyping, 2008)

From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding. - Olivier Muller; Amer Baghdadi; Michel Jézéquel (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Parallelism Efficiency in Convolutional Turbo Decoding. - Olivier Muller; Amer Baghdadi; Michel Jézéquel (EURASIP J. Adv. Signal Process., 2010)

HCM: An abstraction layer for seamless programming of DPR FPGA. - Yan Xu; Olivier Muller; Pierre-Henri Horrein; Frédéric Pétrot (FPL, 2012)

A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints. - Adrien Prost-Boucle; Olivier Muller; Frédéric Rousseau 001 (DSD, 2013)

Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints. - Adrien Prost-Boucle; Olivier Muller; Frédéric Rousseau 001 (J. Syst. Archit., 2014)

Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems. - Alban Bourge; Olivier Muller; Frédéric Rousseau 001 (FCCM, 2015)

A Novel Method for Enabling FPGA Context-Switch (Abstract Only). - Alban Bourge; Olivier Muller; Frédéric Rousseau 001 (FPGA, 2015)

HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. - Simon Pontie; Alban Bourge; Adrien Prost-Boucle; Paolo Maistri; Olivier Muller; Régis Leveugle; Frédéric Rousseau 001 (DSD, 2016)

Demonstration of a context-switch method for heterogeneous reconfigurable systems. - Arief Wicaksana; Alban Bourge; Olivier Muller; Frédéric Rousseau 001 (FPL, 2016)

On-board non-regression test of HLS tools targeting FPGA. - Arief Wicaksana; Adrien Prost-Boucle; Olivier Muller; Frédéric Rousseau 001; Arif Sasongko (RSP, 2016)

Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow. - Alban Bourge; Olivier Muller; Frédéric Rousseau 001 (ACM Trans. Reconfigurable Technol. Syst., 2016)

Prototyping dynamic task migration on heterogeneous reconfigurable systems. - Arief Wicaksana; Alban Bourge; Olivier Muller; Arif Sasongko; Frédéric Rousseau 001 (RSP, 2017)

An FPGA target for the StarPU heterogeneous runtime system. - Georgios Christodoulis; François Broquedis; Olivier Muller; Manuel Selva; Frederic Desprez (ReCoSoC, 2018)

Message-Oriented Devices on FPGAs. - Thomas Baumela; Olivier Gruber; Olivier Muller; Frédéric Pétrot (RSP, 2018)

Efficient Decompression of Binary Encoded Balanced Ternary Sequences. - Olivier Muller; Adrien Prost-Boucle; Alban Bourge; Frédéric Pétrot (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Chisel Usecase: Designing General Matrix Multiply for FPGA. - Bruno Ferres; Olivier Muller; Frédéric Rousseau 001 (ARC, 2020)

(System)Verilog to Chisel Translation for Faster Hardware Design. - Jean Bruant; Pierre-Henri Horrein; Olivier Muller; Tristan Groléat; Frédéric Pétrot (RSP, 2020)

Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. - Bruno Ferres; Olivier Muller; Frédéric Rousseau 001 (RSP, 2021)

Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams. - Arif Sasongko; I. M. Narendra Kumara; Arief Wicaksana; Frédéric Rousseau 001; Olivier Muller (ACM Trans. Reconfigurable Technol. Syst., 2021)

Toward Agile Hardware Designs With Chisel: A Network Use Case. - Jean Bruant; Pierre-Henri Horrein; Olivier Muller; Tristan Groléat; Frédéric Pétrot (IEEE Des. Test, 2022)

Can Knowledge Transfer Techniques Compensate for the Limited Myocardial Infarction Data by Leveraging Hæmodynamics? An in silico Study. - Riccardo Tenderini; Federico Betti; Ortal Yona Senouf; Olivier Muller; Simone Deparis; Annalisa Buffa; Emmanuel Abbe (AIME, 2023)

A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. - Bruno Ferres; Olivier Muller; Frédéric Rousseau 001 (ACM Trans. Design Autom. Electr. Syst., 2023)

Graph Neural Network based Future Clinical Events Prediction from Invasive Coronary Angiography. - Xiaowu Sun; Theofilos Belmpas; Ortal Yona Senouf; Emmanuel Abbe; Pascal Frossard; Bernard De Bruyne; Olivier Muller; Stéphane Fournier; Thabo Mahendiran; Dorina Thanou (ISBI, 2024)

CM-UNet: A Self-Supervised Learning-Based Model for Coronary Artery Segmentation in X-Ray Angiography. - Camille Challier; Xiaowu Sun; Thabo Mahendiran; Ortal Yona Senouf; Bernard De Bruyne; Denise Auberson; Olivier Muller; Stéphane Fournier; Pascal Frossard; Emmanuel Abbe; Dorina Thanou (CoRR, 2025)