Making predictive analog/RF alternate test strategy independent of training set size. - Haithem Ayari; Florence Azaïs; Serge Bernard; Mariane Comte; Vincent Kerzerho; Olivier Potin; Michel Renovell (ITC, 2012)

Smart selection of indirect parameters for DC-based alternate RF IC testing. - Haithem Ayari; Florence Azaïs; Serge Bernard; Mariane Comte; Michel Renovell; Vincent Kerzerho; Olivier Potin; Christophe Kelma (VTS, 2012)

Implementing model redundancy in predictive alternate test to improve test confidence. - Haithem Ayari; Florence Azaïs; Serge Bernard; Mariane Comte; Vincent Kerzerho; Olivier Potin; Michel Renovell (ETS, 2013)

A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. - Vincent Kerzerho; Serge Bernard; Florence Azaïs; Mariane Comte; Olivier Potin; Chuan Shan; G. Bontorin; Michel Renovell (Microelectron. J., 2013)

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. - Jean-Max Dutertre; Rodrigo Possamai Bastos; Olivier Potin; Marie-Lise Flottes; Bruno Rouzeyre; Giorgio Di Natale (Microelectron. Reliab., 2013)

Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. - Jean-Max Dutertre; Rodrigo Possamai Bastos; Olivier Potin; Marie-Lise Flottes; Bruno Rouzeyre; Giorgio Di Natale; Alexandre Sarafianos (Microelectron. Reliab., 2014)

Filtering-based CPA: a successful side-channel attack against desynchronization countermeasures. - Karim M. Abdellatif; Damien Couroussé; Olivier Potin; Philippe Jaillon (CS2@HiPEAC, 2017)

Runtime Code Polymorphism as a Protection Against Side Channel Attacks. - Damien Couroussé; Thierno Barry; Bruno Robisson; Philippe Jaillon; Olivier Potin; Jean-Louis Lanet (IACR Cryptol. ePrint Arch., 2017)

All paths lead to Rome: Polymorphic Runtime Code Generation for Embedded Systems. - Damien Couroussé; Thierno Barry; Bruno Robisson; Nicolas Belleville; Philippe Jaillon; Olivier Potin; Hélène Le Bouder; Jean-Louis Lanet; Karine Heydemann (CS2@HiPEAC, 2018)

Assessing body built-in current sensors for detection of multiple transient faults. - Raphael Andreoni Camponogara Viera; Jean-Max Dutertre; Marie-Lise Flottes; Olivier Potin; Giorgio Di Natale; Bruno Rouzeyre; Rodrigo Possamai Bastos (Microelectron. Reliab., 2018)

Experimental Analysis of the Laser-Induced Instruction Skip Fault Model. - Jean-Max Dutertre; Timothée Riom; Olivier Potin; Jean-Baptiste Rigaud (NordSec, 2019)

Experimental Analysis of the Electromagnetic Instruction Skip Fault Model. - Alexandre Menu; Jean-Max Dutertre; Olivier Potin; Jean-Baptiste Rigaud; Jean-Luc Danger (DTIS, 2020)

Combined Fault Injection and Real-Time Side-Channel Analysis for Android Secure-Boot Bypassing. - Clément Fanjas; Clément Gaine; Driss Aboulkassimi; Simon Pontié; Olivier Potin (CARDIS, 2022)

A CFI Verification System based on the RISC-V Instruction Trace Encoder. - Anthony Zgheib; Olivier Potin; Jean-Baptiste Rigaud; Jean-Max Dutertre (DSD, 2022)

CMOS/STT-MRAM Based Ascon LWC: a Power Efficient Hardware Implementation. - Nathan Roussel; Olivier Potin; Gregory di Pendina; Jean-Max Dutertre; Jean-Baptiste Rigaud (ICECS 2022, 2022)

Real-Time Frequency Detection to Synchronize Fault Injection on System-on-Chip. - Clément Fanjas; Clément Gaine; Driss Aboulkassimi; Simon Pontié; Olivier Potin (IACR Cryptol. ePrint Arch., 2022)

A CCFI Verification Scheme Based on the RISC-V Trace Encoder. - Anthony Zgheib; Olivier Potin; Jean-Baptiste Rigaud; Jean-Max Dutertre (COSADE, 2023)

Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation. - Nathan Roussel; Olivier Potin; Jean-Max Dutertre; Jean-Baptiste Rigaud (DATE, 2023)

Software-Only Control-Flow Integrity Against Fault Injection Attacks. - François Bonnal; Vincent Dupaquis; Olivier Potin; Jean-Max Dutertre (DSD, 2023)

Fault Injection on Embedded Neural Networks: Impact of a Single Instruction Skip. - Clément Gaine; Pierre-Alain Moëllic; Olivier Potin; Jean-Max Dutertre (DSD, 2023)

Lightweight Countermeasures Against Original Linear Code Extraction Attacks on a RISC-V Core. - Théophile Gousselot; Olivier Thomas; Jean-Max Dutertre; Olivier Potin; Jean-Baptiste Rigaud (HOST, 2023)

CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core. - Anthony Zgheib; Olivier Potin; Jean-Baptiste Rigaud; Jean-Max Dutertre (HOST, 2023)

Experimental EMFI detection on a RISC-V core using the Trace Verifier solution. - Anthony Zgheib; Olivier Potin; Jean-Baptiste Rigaud; Jean-Max Dutertre (Microprocess. Microsystems, 2023)

Using a Performance Model to Implement a Superscalar CVA6. - Côme Allart; Jean-Roch Coulon; André Sintzoff; Olivier Potin; Jean-Baptiste Rigaud (CF (Companion), 2024)

Modular Multiplication in the AMNS Representation: Hardware Implementation. - Louis Noyez; Nadia El Mrabet; Olivier Potin; Pascal Véron (SAC (2), 2024)

Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2. - Louis Noyez; Nadia El Mrabet; Olivier Potin; Pascal Véron (ACM Trans. Reconfigurable Technol. Syst., 2024)

Code Encryption for Confidentiality and Execution Integrity Down to Control Signals. - Théophile Gousselot; Jean-Max Dutertre; Olivier Potin; Jean-Baptiste Rigaud (HOST, 2025)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture. - Riccardo Tedeschi; Gianmarco Ottavi; Côme Allart; Nils Wistoff; Zexin Fu; Filippo Grillotti; Fabio De Ambroggi; Elio Guidetti; Jean-Baptiste Rigaud; Olivier Potin; Jean-Roch Coulon; César Fuguet; et al. (CoRR, 2025)