A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS. - Raguram Damodaran; Timothy Anderson; Sanjive Agarwala; Rama Venkatasubramanian; Michael Gill; Dhileep Gopalakrishnan; Anthony M. Hill; Abhijeet Chachad; Dheera Balasubramanian; Naveen Bhoria; Jonathan Tran; Duc Bui; et al. (VLSI Design, 2012)

State Retention Validation of C66X DSP Core. - Rama Venkatasubramanian; Oluleye Olorode; Abhishek Arun (MTV, 2013)

Replacement techniques for improving performance in sub-block caches. - Oluleye Olorode; Mehrdad Nourani (ACSSC, 2014)

Static power reduction in caches using deterministic naps. - Oluleye Olorode; Mehrdad Nourani (ANCS, 2014)

Improving Performance in Sub-Block Caches with Optimized Replacement Policies. - Oluleye Olorode; Mehrdad Nourani (ACM J. Emerg. Technol. Comput. Syst., 2015)

Improving Cache Power and Performance Using Deterministic Naps and Early Miss Detection. - Oluleye Olorode; Mehrdad Nourani (IEEE Trans. Multi Scale Comput. Syst., 2015)