Direct residue-to-analog conversion scheme based on Chinese Remainder Theorem. - Omar Abdelfattah; Andraws I. Swidan; Zeljko Zilic (ICECS, 2010)

A 30-40 GHz fractional-N frequency synthesizer development using a Verilog-A high-level design methodology. - George Gal; Omar Abdelfattah; Gordon W. Roberts (MWSCAS, 2012)

A simple analog CMOS design tool using transistor dimension-independent parameters. - Omar Abdelfattah; Ishiang Shih; Gordon W. Roberts (ISCAS, 2013)

Analytical comparison between passive loop filter topologies for frequency synthesizer PLLs. - Omar Abdelfattah; Ishiang Shih; Gordon W. Roberts (NEWCAS, 2013)

Optimization of LC-VCO tuning range under different inductor/varactor losses limitations. - Omar Abdelfattah; Ishiang Shih; Gordon W. Roberts; Yi-Chi Shih (CCECE, 2014)

A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS. - Omar Abdelfattah; Gordon W. Roberts; Ishiang Shih; Yi-Chi Shih (ISCAS, 2015)

A 0.55-V 1-GHz frequency synthesizer PLL for ultra-low-voltage ultra-low-power applications. - Omar Abdelfattah; Ishiang Shih; Gordon W. Roberts; Yi-Chi Shih (LASCAS, 2015)

A 0.6V-supply bandgap reference in 65 nm CMOS. - Omar Abdelfattah; Ishiang Shih; Gordon W. Roberts; Yi-Chi Shih (NEWCAS, 2015)

An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range. - Omar Abdelfattah; Gordon W. Roberts; Ishiang Shih; Yi-Chi Shih (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs. - Omar Abdelfattah; George Gal; Gordon W. Roberts; Ishiang Shih; Yi-Chi Shih (IEEE Trans. Very Large Scale Integr. Syst., 2016)